Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9543037 | Semiconductor device having electrical fuse and control method thereof | Daiki Nakashima | 2017-01-10 |
| 9230686 | Semiconductor device having roll call circuit | Hiroyuki Yamamoto | 2016-01-05 |
| 8699256 | Semiconductor device having nonvolatile memory elements | Hiroki Fujisawa | 2014-04-15 |
| 8633758 | Semiconductor device having boosting circuit | Hiroki Fujisawa, Hitoshi Tanaka | 2014-01-21 |
| 8270237 | Semiconductor device, relief-address-information writing device, and relief-address-information writing method | — | 2012-09-18 |
| 7940583 | Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address | Yoshiro Riho, Jun Suzuki, Yasuhiro Matsumoto, Hiromasa Noda, Yasuji Koshikawa | 2011-05-10 |
| 7940587 | Semiconductor memory device and test method thereof | Jun Suzuki | 2011-05-10 |
| 7580321 | Synchronous semiconductor memory device | Hiroki Fujisawa, Koji Kuroki | 2009-08-25 |
| 7345950 | Synchronous semiconductor memory device | Hiroki Fujisawa, Koji Kuroki | 2008-03-18 |
| 7085192 | Semiconductor integrated circuit device | Hiroki Fujisawa | 2006-08-01 |
| 6954386 | Boosted potential generation circuit and control method | Seiji Narui, Kenji Mae, Makoto Morino | 2005-10-11 |
| 6934214 | Semiconductor memory device having a hierarchical I/O structure | Hiroki Fujisawa, Koichiro Ninomiya | 2005-08-23 |
| 6765844 | Semiconductor memory device having a hierarchical I/O structure | Hiroki Fujisawa, Koichiro Ninomiya | 2004-07-20 |
| 6665203 | Semiconductor memory device having a hierarchial I/O strucuture | Hiroki Fujisawa, Koichiro Ninomiya | 2003-12-16 |
| 5905685 | Dynamic memory | Masayuki Nakamura, Masatoshi Hasegawa, Seiji Narui, Yousuke Tanaka, Shinichi Miyatake +1 more | 1999-05-18 |