Issued Patents All Time
Showing 76–92 of 92 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6754746 | Memory array with read/write methods | Wingyu Leung, Fu-Chieh Hsu | 2004-06-22 |
| 6680859 | Logic process DRAM | Peter Wung Lee, Sehat Sutardja | 2004-01-20 |
| 6570781 | Logic process DRAM | Peter Wung Lee, Sehat Sutardja | 2003-05-27 |
| 6393504 | Dynamic address mapping and redundancy in a modular memory device | Wingyu Leung, Fu-Chieh Hsu | 2002-05-21 |
| 6272577 | Data processing system with master and slave devices and asymmetric signal swing bus | Wingyu Leung, Fu-Chieh Hsu | 2001-08-07 |
| 5737587 | Resynchronization circuit for circuit module architecture | Wingyu Leung, Fu-Chieh Hsu | 1998-04-07 |
| 5729152 | Termination circuits for reduced swing signal lines and methods for operating same | Wingyu Leung, Fu-Chieh Hsu | 1998-03-17 |
| 5659550 | Latent defect handling in EEPROM devices | Sanjay Mehrotra, George Samachisa, Stephen J. Gross | 1997-08-19 |
| 5655113 | Resynchronization circuit for a memory system and method of operating same | Wingyu Leung, Fu-Chieh Hsu | 1997-08-05 |
| 5498990 | Reduced CMOS-swing clamping circuit for bus lines | Wingyu Leung, Fu-Chieh Hsu | 1996-03-12 |
| 5432823 | Method and circuitry for minimizing clock-data skew in a bus system | James A. Gasbarro, Mark A. Horowitz, Richard M. Barth, Wingyu Leung, Paul Michael Farmwald | 1995-07-11 |
| 5428621 | Latent defect handling in EEPROM devices | Sanjay Mehrotra, George Samachisa, Stephen J. Gross | 1995-06-27 |
| 5355391 | High speed bus system | Mark A. Horowitz | 1994-10-11 |
| 5172338 | Multi-state EEprom read and write circuits and techniques | Sanjay Mehrotra, Eliyahou Harari | 1992-12-15 |
| 5163021 | Multi-state EEprom read and write circuits and techniques | Sanjay Mehrotra, Eliyahou Harari | 1992-11-10 |
| 4916337 | TTL to CMOS logic level translator | Wingyu Leung | 1990-04-10 |
| 4797856 | Self-limiting erase scheme for EEPROM | Duane H. Oto, Simon Tam | 1989-01-10 |