QY

Qiong Yu

CC China Wafer Level Csp Co.: 12 patents #3 of 26Top 15%
Lsi Logic: 3 patents #574 of 1,957Top 30%
EU East China Normal University: 1 patents #33 of 168Top 20%
📍 Suzhou, CA: #46 of 94 inventorsTop 50%
Overall (All Time): #294,679 of 4,157,543Top 8%
16
Patents All Time

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDate
10529758 Packaging method and packaging structure Zhiqi Wang, Wei-Chung Wang 2020-01-07
10133907 Fingerprint recognition chip packaging structure and packaging method Zhiqi Wang, Wei-Chung Wang 2018-11-20
10126151 Wafer-level chip package structure and packaging method Zhiqi Wang, Wei-Chung Wang 2018-11-13
10108837 Fingerprint recognition chip packaging structure and packaging method Zhiqi Wang, Wei-Chung Wang 2018-10-23
10096643 Fingerprint recognition chip packaging structure and packaging method Zhiqi Wang, Wei-Chung Wang 2018-10-09
10090217 Chip packaging method and package structure Zhiqi Wang, Wei-Chung Wang 2018-10-02
9748162 Chip to wafer package with top electrodes and method of forming Zhiqi Wang, Junjie Li, Ying Yang, Wei-Chung Wang 2017-08-29
9601531 Wafer-level packaging structure for image sensors with packaging cover dike structures corresponding to scribe line regions Zhiqi Wang, Wei-Chung Wang 2017-03-21
9455298 Wafer-level packaging method of BSI image sensors having different cutting processes Zhi Wang, Wei-Chung Wang 2016-09-27
9305961 Wafer-level packaging method of BSI image sensors having different cutting processes Zhi Wang, Wei-Chung Wang 2016-04-05
9299735 Image sensor package structure and method Zhiqi Wang, Wei-Chung Wang 2016-03-29
9231018 Wafer level packaging structure for image sensors and wafer level packaging method for image sensors Zhiqi Wang, Wei-Chung Wang 2016-01-05
8748669 Process for producing aldehydes or ketones by oxidizing alcohols with oxygen Shengming Ma, Jinxian Liu, Jinqiang Kuang, Yu Liu, Yuli Wang +7 more 2014-06-10
6829754 Method and system for checking for power errors in ASIC designs Radoslav Ratchkov, Bo Shen, Prasad Subbarao, Thomas Antisseril, Charutosh Dixit +1 more 2004-12-07
6560761 Method of datapath cell placement for bitwise and non-bitwise integrated circuit designs Alexander Tetelbuam 2003-05-06
6496967 Method of datapath cell placement for an integrated circuit Alexander Tetelbaum 2002-12-17