Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8671395 | Adaptive deadend avoidance in constrained simulation | Jun Yuan, Akok Jain, Manpreet Reehal | 2014-03-11 |
| 8104001 | Automated debugging method for over-constrained circuit verification environment | Amir Lehavot, Joezac John Zachariah, Jose Barandiaran, Axel Scherer | 2012-01-24 |
| 8099695 | Automated debugging method and system for over-constrained circuit verification environment | Amir Lehavot, Joezac John Zachariah, Jose Barandiaran, Axel Scherer | 2012-01-17 |
| 8099696 | Method for providing information associated with an over-constrained event in verification of a circuit design | Amir Lehavot, Joezac John Zachariah, Jose Barandiaran, Axel Scherer | 2012-01-17 |
| 7984401 | Method for checking a status of a signal port to identify an over-constrained event | Amir Lehavot, Joezac John Zachariah, Jose Barandiaran, Axel Scherer | 2011-07-19 |
| 7810056 | Method and system for implementing context aware synthesis of assertions | Tarun Garg | 2010-10-05 |
| 7712060 | Method and system for handling assertion libraries in functional verification | Tarun Garg, Pratik Mahajan, Mohamad Shaved | 2010-05-04 |
| 7428712 | Design optimization using approximate reachability analysis | Ravi Prakash, Alok Jain, Kavita Ravi | 2008-09-23 |
| 7386813 | Transformation of simple subset of PSL into SERE implication formulas for verification with model checking and simulation engines using semantic preserving rewrite rules | Tarun Garg | 2008-06-10 |