MS

Mohamad Shaved

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
Overall (All Time): #3,287,709 of 4,157,543Top 80%
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Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
7712060 Method and system for handling assertion libraries in functional verification Tarun Garg, Vinaya Kumar Singh, Pratik Mahajan 2010-05-04