AL

Amir Lehavot

CS Cadence Design Systems: 4 patents #399 of 2,263Top 20%
TJ Tellabs San Jose: 2 patents #12 of 55Top 25%
UN Unknown: 1 patents #29,356 of 83,584Top 40%
🗺 California: #82,707 of 386,348 inventorsTop 25%
Overall (All Time): #745,405 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDate
8165112 Apparatus and method for a fault-tolerant scalable switch fabric with quality-of-service (QOS) support Raghavan Menon, Adam Goldstein, Mark Griswold, Mitri Halabi, Mohammad K. Issa +2 more 2012-04-24
8104001 Automated debugging method for over-constrained circuit verification environment Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Scherer 2012-01-24
8099696 Method for providing information associated with an over-constrained event in verification of a circuit design Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Scherer 2012-01-17
8099695 Automated debugging method and system for over-constrained circuit verification environment Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Scherer 2012-01-17
7984401 Method for checking a status of a signal port to identify an over-constrained event Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Scherer 2011-07-19
7505458 Apparatus and method for a fault-tolerant scalable switch fabric with quality-of-service (QOS) support Raghavan Menon, Adam Goldstein, Mark Griswold, Mitri Halabi, Mohammad K. Issa +2 more 2009-03-17
5825217 Low power accelerated switching for MOS circuits 1998-10-20