Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8104001 | Automated debugging method for over-constrained circuit verification environment | Amir Lehavot, Vinaya Kumar Singh, Jose Barandiaran, Axel Scherer | 2012-01-24 |
| 8099695 | Automated debugging method and system for over-constrained circuit verification environment | Amir Lehavot, Vinaya Kumar Singh, Jose Barandiaran, Axel Scherer | 2012-01-17 |
| 8099696 | Method for providing information associated with an over-constrained event in verification of a circuit design | Amir Lehavot, Vinaya Kumar Singh, Jose Barandiaran, Axel Scherer | 2012-01-17 |
| 7984401 | Method for checking a status of a signal port to identify an over-constrained event | Amir Lehavot, Vinaya Kumar Singh, Jose Barandiaran, Axel Scherer | 2011-07-19 |