Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8639510 | Acoustic scoring unit implemented on a single FPGA or ASIC | Kai Yu | 2014-01-28 |
| 8463610 | Hardware-implemented scalable modular engine for low-power speech recognition | Patrick J. Bourke | 2013-06-11 |
| 8352265 | Hardware implemented backend search engine for a high-rate speech recognition system | Edward C. Lin | 2013-01-08 |
| 8290761 | Method and apparatus for rapidly modeling and simulating intra-die statistical variations in integrated circuits using compressed parameter models | Amith Singhee, Sonia Singhal | 2012-10-16 |
| 8155938 | Method and apparatus for sampling and predicting rare events in complex electronic devices, circuits and systems | Amith Singhee | 2012-04-10 |
| 7920992 | Method and system for modeling uncertainties in integrated circuits, systems, and fabrication processes | James Ma, Claire F. Fang, Amith Singhee | 2011-04-05 |
| 7093220 | Method for generating constrained component placement for integrated circuits and packages | Elias Lee Fallon | 2006-08-15 |
| 7058916 | Method for automatically sizing and biasing circuits by means of a database | Rodney Phelps, Ronald A. Rohrer, Anthony James Gadient, L. Richard Carley | 2006-06-06 |
| 6957400 | Method and apparatus for quantifying tradeoffs for multiple competing goals in circuit design | Hongzhou Liu, Rodney Phelps | 2005-10-18 |
| 6918102 | Method and apparatus for exact relative positioning of devices in a semiconductor circuit layout | Regis Colwell, Elias Lee Fallon | 2005-07-12 |
| 6874133 | Integrated circuit design layout compaction method | Prakash Gopalakrishnan, Elias Lee Fallon | 2005-03-29 |
| 6711725 | Method of creating conformal outlines for use in transistor level semiconductor layouts | Donald Benson Reaves, Elias Lee Fallon | 2004-03-23 |