Issued Patents All Time
Showing 76–96 of 96 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6944841 | Method and apparatus for proportionate costing of vias | Steven Teig | 2005-09-13 |
| 6938234 | Method and apparatus for defining vias | Steven Teig, Etienne Jacques | 2005-08-30 |
| 6931608 | Method and apparatus for determining viability of path expansions | Steven Teig | 2005-08-16 |
| 6931615 | Method and apparatus for identifying a path between source and target states | Steven Teig | 2005-08-16 |
| 6928633 | IC layout having topological routes | Steven Teig | 2005-08-09 |
| 6915500 | Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated Euclidean wiring | Steven Teig | 2005-07-05 |
| 6915499 | Method and apparatus for propagating a piecewise linear function to a line | Steven Teig | 2005-07-05 |
| 6898772 | Method and apparatus for defining vias | Steven Teig | 2005-05-24 |
| 6898773 | Method and apparatus for producing multi-layer topological routes | Steven Teig | 2005-05-24 |
| 6895569 | IC layout with non-quadrilateral Steiner points | Steven Teig, Akira Fujimura | 2005-05-17 |
| 6895567 | Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs | Steven Teig | 2005-05-17 |
| 6889372 | Method and apparatus for routing | Steven Teig | 2005-05-03 |
| 6889371 | Method and apparatus for propagating a function | Steven Teig | 2005-05-03 |
| 6886149 | Method and apparatus for routing sets of nets | Steven Teig | 2005-04-26 |
| 6882055 | Non-rectilinear polygonal vias | Steven Teig | 2005-04-19 |
| 6877146 | Method and apparatus for routing a set of nets | Steven Teig | 2005-04-05 |
| 6859916 | Polygonal vias | Steven Teig | 2005-02-22 |
| 6829757 | Method and apparatus for generating multi-layer routes | Steven Teig | 2004-12-07 |
| 6769105 | Method and arrangement for layout and manufacture of gridded non manhattan semiconductor integrated circuits | Steven Teig | 2004-07-27 |
| 6711727 | Method and arrangement for layout and manufacture of gridless nonManhattan semiconductor integrated circuits | Steven Teig | 2004-03-23 |
| 6526555 | Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compaction | Steven Teig | 2003-02-25 |