AC

Andrew Caldwell

CS Cadence Design Systems: 53 patents #5 of 2,263Top 1%
TA Tabula: 30 patents #5 of 42Top 15%
IN Intel: 11 patents #3,700 of 30,777Top 15%
CS Candence Design Systems: 1 patents #1 of 20Top 5%
🗺 California: #2,419 of 386,348 inventorsTop 1%
Overall (All Time): #15,839 of 4,157,543Top 1%
96
Patents All Time

Issued Patents All Time

Showing 51–75 of 96 patents

Patent #TitleCo-InventorsDate
7089524 Topological vias route wherein the topological via does not have a coordinate within the region Steven Teig 2006-08-08
7080329 Method and apparatus for identifying optimized via locations Steven Teig 2006-07-18
7073151 Method and apparatus for identifying a path between a set of source states and a set of target states in a triangulated space Steven Teig 2006-07-04
7069531 Method and apparatus for identifying a path between source and target states in a space with more than two dimensions Steven Teig 2006-06-27
7069530 Method and apparatus for routing groups of paths Steven Teig 2006-06-27
7058917 Method and apparatus for specifying a cost function that represents the estimated distance between an external state and a set of states in a space Steven Teig 2006-06-06
7051298 Method and apparatus for specifying a distance between an external state and a set of states in space Steven Teig 2006-05-23
7047512 Method and apparatus for specifying a cost function that represents the estimated distance between an external state and a set of states in a space Steven Teig 2006-05-16
7036105 Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC's Steven Teig, Etienne Jacques 2006-04-25
7032201 Method and apparatus for decomposing a region of an integrated circuit layout Steven Teig 2006-04-18
7020863 Method and apparatus for decomposing a region of an integrated circuit layout Steven Teig 2006-03-28
7013448 Method and apparatus for propagating cost functions Steven Teig 2006-03-14
7003752 Method and apparatus for routing Steven Teig, Jonathan Frankle, Etienne Jacques 2006-02-21
7000209 Method and apparatus for propagating a piecewise linear function to a surface Steven Teig 2006-02-14
6988257 Method and apparatus for routing Steven Teig, Jonathan Frankle, Etienne Jacques 2006-01-17
6986117 Method and apparatus for identifying a path between source and target states Steven Teig 2006-01-10
6978432 Method and apparatus for propagating a piecewise linear function to a point Steven Teig 2005-12-20
6976238 Circular vias and interconnect-line ends Steven Teig, Akira Fujimura 2005-12-13
6973634 IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout Steven Teig, Etienne Jacques 2005-12-06
6957411 Gridless IC layout and method and apparatus for generating such a layout Steven Teig, Etienne Jacques 2005-10-18
6957409 Method and apparatus for generating topological routes for IC layouts using perturbations Steven Teig 2005-10-18
6957408 Method and apparatus for routing nets in an integrated circuit layout Steven Teig, Etienne Jacques 2005-10-18
6951006 Decomposing IC regions and embedding routes Steven Teig 2005-09-27
6951005 Method and apparatus for selecting a route for a net based on the impact on other nets Steven Teig 2005-09-27
6948144 Method and apparatus for costing a path expansion Steven Teig 2005-09-20