Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7961781 | Electronic dispersion compensation utilizing interleaved architecture and channel identification for assisting timing recovery | Vivek Telang, Vasudevan Parthasarathy, Sudeep Bhoja, Hong Chen, Afshin Momtaz +3 more | 2011-06-14 |
| 7765343 | Method and system for robust elastic FIFO (EFIFO) in a port bypass controller | Chung-Jue Chen, Jay Proano, Rajesh Satapathy, Steve Thomas | 2010-07-27 |
| 7702010 | System for monitoring the quality of a communications channel with mirror receivers | Jay Proano, Howard Baumer, Chung-Jue Chen, Vasudevan Parthasarathy, Rajesh Satapathy +1 more | 2010-04-20 |
| 7676158 | Method and system for optimum channel equalization from a SerDes to an optical module | — | 2010-03-09 |
| 7664170 | Bit stream linear equalizer with AGC loop | Davide Tonietto | 2010-02-16 |
| 7643543 | Multiple high-speed bit stream interface circuit | — | 2010-01-05 |
| 7577171 | Source centered clock supporting quad 10 GBPS serial interface | Mohammad Nejad, Guangming Yin | 2009-08-18 |
| 7515629 | Conditioning circuit that spectrally shapes a serviced bit stream | Davide Tonietto | 2009-04-07 |
| 7492783 | Method and system for LIPf7 origination detection and LIPf8 suppression in a port bypass controller | Chung-Jue Chen, Jay Proano, Rajesh Satapathy, Steve Thomas | 2009-02-17 |
| 7451362 | Method and system for onboard bit error rate (BER) estimation in a port bypass controller | Chung-Jue Chen, Jay Proano, Rajesh Satapathy, Steve Thomas | 2008-11-11 |
| 7443890 | Multi-stage multiplexing chip set having switchable forward/reverse clock relationship | Mohammad Nejad | 2008-10-28 |
| 7349450 | Multi-stage high speed bit stream demultiplexer chip set having switchable master/slave relationship | Mohammad Nejad, Rajagopal Anantha Rao | 2008-03-25 |
| 7346082 | High-speed serial bit stream multiplexing and demultiplexing integrated circuits | Mohammad Nejad, Guangming Yin | 2008-03-18 |
| 7339986 | Method of monitoring the quality of a communications channel | Jay Proano, Howard Baumer, Chung-Jue Chen, Vasudevan Parthasarathy, Rajesh Satapathy +1 more | 2008-03-04 |
| 7333537 | System for monitoring the quality of a communications channel with mirror receivers | Jay Proano, Howard Baumer, Chung-Jue Chen, Vasudevan Parthasarathy, Rajesh Satapathy +1 more | 2008-02-19 |
| 7321612 | Bit stream conditioning circuit having adjustable PLL bandwidth | Davide Tonietto | 2008-01-22 |
| 7317769 | Bit stream conditioning circuit having adjustable input sensitivity | Davide Tonietto | 2008-01-08 |
| 7313097 | Loop back testing structure for high-speed serial bit stream TX and RX chip set | Bo Zhang | 2007-12-25 |
| 7257154 | Multiple high-speed bit stream interface circuit | — | 2007-08-14 |
| 7206337 | Bit stream conditioning circuit having output pre-emphasis | Davide Tonietto | 2007-04-17 |
| 6546345 | System and method for measuring extinction ratio and deterministic jitter | — | 2003-04-08 |