Issued Patents All Time
Showing 25 most recent of 118 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12401335 | Integrated transimpedance amplifier with a digital signal processor for high-speed optical receivers | Jiawen Zhang, Delong Cui, Kun Chuai, Jun Cao | 2025-08-26 |
| 12360552 | Synchronization of devices with a gapped reference clock | Hongtao Jiang, Jun Cao, Armond Hairapetian, Kang Xiao | 2025-07-15 |
| 11722109 | Integrated transimpedance amplifier with a digital signal processor for high-speed optical receivers | Jiawen Zhang, Delong Cui, Kun Chuai, Jun Cao | 2023-08-08 |
| 11502690 | Power supply generation for transmitter | Alireza Nilchi, Anand J. Vasani, Arvindh Iyer, Jun Cao | 2022-11-15 |
| 10476516 | Pre-driver peaking technique for high-speed DACs | Kun Chuai, Jun Cao, Seong Ho Lee, Burak Catli, Anand J. Vasani +1 more | 2019-11-12 |
| 10033520 | Multilane serdes clock and data skew alignment for multi-standard support | Adesh Garg, Jun Cao, Namik Kocaman, Kuo-J Huang, Delong Cui | 2018-07-24 |
| 10014846 | Increasing output amplitude of a voltage-mode driver in a low supply voltage technology | Adesh Garg | 2018-07-03 |
| 9685969 | Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration | Adesh Garg, Ali Nazemi, Anand J. Vasani, Hyo Gyuem Rhew, Jiawen Zhang +3 more | 2017-06-20 |
| 9413381 | High-speed, low-power reconfigurable voltage-mode DAC-driver | Anand J. Vasani, Ali Nazemi, Jun Cao | 2016-08-09 |
| 9344268 | Phase alignment architecture for ultra high-speed data path | Ali Nazemi, Burak Catli, Wayne W. Wong, Kangmin Hu, Hyo Gyuem Rhew +3 more | 2016-05-17 |
| 9325316 | Low-power high swing CML driver with independent common-mode and swing control | Amr Amin Hafez Amin Abou-El-Sonoun, Ramy Awad, Mohammed Abdul-Latif, Adesh Garg, Henry Arnold Park +3 more | 2016-04-26 |
| 9306621 | Transceiver including a high latency communication channel and a low latency communication channel | Heng Zhang, Mehdi Khanpour, Jun Cao, Chang Liu | 2016-04-05 |
| 9281828 | Reference-less voltage controlled oscillator (VCO) calibration | Mahyar Kargar, Siavash Fallahi, Namik Kocaman | 2016-03-08 |
| 9246670 | Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDes | Mahmoud Reza Ahmadi, Siavash Fallahi, Tamer Mohammed Ali, Ali Nazemi, Hassan Maarefi +1 more | 2016-01-26 |
| 9231571 | Resonant clock amplifier with a digitally tunable delay | Bharath Raghavan, Jun Cao | 2016-01-05 |
| 9197214 | High speed level shifter with amplitude servo loop | Ali Nazemi, Kangmin Hu, Jun Cao | 2015-11-24 |
| 9136797 | Adaptive harmonic distortion suppression in an amplifier utilizing negative gain | Kuo-J Huang, Delong Cui, Jun Cao, Iuri Mehr, Ramon A. Gomez | 2015-09-15 |
| 9100167 | Multilane SERDES clock and data skew alignment for multi-standard support | Adesh Garg, Jun Cao, Namik Kocaman, Kuo-J Huang, Delong Cui | 2015-08-04 |
| 9077328 | Method and apparatus for reference-less repeater with digital control | Magesh Valliappan, Namik Kocaman, Vasudevan Parthasarathy | 2015-07-07 |
| 9065464 | Phase adjustment scheme for time-interleaved ADCS | Heng Zhang, Delong Cui, Jun Cao | 2015-06-23 |
| RE45557 | Configurable voltage controlled oscillator system and method including dividing forming a portion of two or more divider paths | Mario Caresosa, Namik Kocaman | 2015-06-09 |
| 9024659 | Method and apparatus for passive equalization and slew-rate control | Tamer Mohammed Ali, Hassan Maarefi, Mahmoud Reza Ahmadi | 2015-05-05 |
| 9001869 | Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDes | Mahmoud Reza Ahmadi, Siavash Fallahi, Tamer Mohammed Ali, Ali Nazemi, Hassan Maarefi +1 more | 2015-04-07 |
| 8964923 | Low latency high bandwidth CDR architecture | Anand J. Vasani, Jun Cao | 2015-02-24 |
| 8964907 | Multi-protocol communications receiver with shared analog front-end | Vivek Telang, Hong Chen, Vasudevan Parthasarathy, Jun Cao, Ali Ghiasi +1 more | 2015-02-24 |