| 12185052 |
Earphone control method, earphone box, earphone and storage medium |
Bin Bai, Minghui Hu, Xuemei Wang, Yanhong Yao, Xiaokang Li +3 more |
2024-12-31 |
|
| 9998099 |
Feed-forward bias circuit |
Wenjun Su, Chulkyu Lee, Le Zhang |
2018-06-12 |
$8,223,000 |
| 9401594 |
Surge protection for differential input/output interfaces |
Quanqing Zhu |
2016-07-26 |
$14,537,000 |
| 8779859 |
Multi-cascode amplifier bias techniques |
Wenjun Su, Chiewcharn Narathong, Aristotele Hadjichristos |
2014-07-15 |
$5,442,000 |
| 8750338 |
Symmetrical clock distribution in multi-stage high speed data conversion circuits |
Bo Zhang, Mohammad Nejad, Jun Cao |
2014-06-10 |
$3,190,000 |
| 8259762 |
Symmetrical clock distribution in multi-stage high speed data conversion circuits |
Bo Zhang, Mohammad Nejad, Jun Cao |
2012-09-04 |
$5,213,000 |
| 7974337 |
High speed receive equalizer architecture |
Afshin Momtaz, Mario Caresosa, David Chung, Davide Tonietto, Bruce J. Currivan +2 more |
2011-07-05 |
$3,696,000 |
| 7864909 |
Signal delay structure in high speed bit stream demultiplexer |
Jun Cao |
2011-01-04 |
$5,121,000 |
| 7834790 |
Communication device including a power reduction mechanism |
— |
2010-11-16 |
$6,049,000 |
| 7778288 |
Symmetrical clock distribution in multi-stage high speed data conversion circuits |
Bo Zhang, Mohammad Nejad, Jun Cao |
2010-08-17 |
$4,359,000 |
| 7623600 |
High speed receive equalizer architecture |
Afshin Momtaz, Mario Caresosa, David Chung, Davide Tonietto, Bruce J. Currivan +2 more |
2009-11-24 |
$15,525,000 |
| 7616725 |
Signal delay structure in high speed bit stream demultiplexer |
Jun Cao |
2009-11-10 |
$5,358,000 |
| 7577171 |
Source centered clock supporting quad 10 GBPS serial interface |
Mohammad Nejad, Ali Ghiasi |
2009-08-18 |
$16,761,000 |
| 7511582 |
Voltage controlled oscillator for use in phase locked loop |
— |
2009-03-31 |
$9,903,000 |
| 7449964 |
System and method for tuning output drivers using voltage controlled oscillator capacitor settings |
Bo Zhang, Ichiro Fujimori |
2008-11-11 |
$3,508,000 |
| 7386084 |
Method and system for pattern-independent phase adjustment in a clock and data recovery (CDR) circuit |
— |
2008-06-10 |
$7,118,000 |
| 7346082 |
High-speed serial bit stream multiplexing and demultiplexing integrated circuits |
Ali Ghiasi, Mohammad Nejad |
2008-03-18 |
$6,864,000 |
| 7319706 |
Symmetrical clock distribution in multi-stage high speed data conversion circuits |
Bo Zhang, Mohammad Nejad, Jun Cao |
2008-01-15 |
$11,799,000 |
| 7319351 |
Delay generator with symmetric signal paths |
Bo Zhang |
2008-01-15 |
$11,799,000 |
| 7289543 |
System and method for testing the operation of a DLL-based interface |
Bo Zhang |
2007-10-30 |
$15,616,000 |
| 7262659 |
Adaptable voltage control for a variable gain amplifier |
Mario Caresosa |
2007-08-28 |
$9,767,000 |
| 7142013 |
One-level zero-current-state exclusive or (XOR) gate |
— |
2006-11-28 |
$10,330,000 |
| 7135926 |
Adaptable voltage control for a variable gain amplifier |
Mario Caresosa |
2006-11-14 |
$9,916,000 |
| 7109799 |
Current-controlled CMOS wideband data amplifier circuits |
Jun Cao |
2006-09-19 |
$6,415,000 |
| 7098692 |
Switchable power domains for 1.2v and 3.3v pad voltages |
Sridevi R. Joshi, Mohammad Nejad, Daniel Schoch |
2006-08-29 |
$7,729,000 |
