Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12185052 | Earphone control method, earphone box, earphone and storage medium | Bin Bai, Minghui Hu, Xuemei Wang, Yanhong Yao, Xiaokang Li +3 more | 2024-12-31 |
| 9998099 | Feed-forward bias circuit | Wenjun Su, Chulkyu Lee, Le Zhang | 2018-06-12 |
| 9401594 | Surge protection for differential input/output interfaces | Quanqing Zhu | 2016-07-26 |
| 8779859 | Multi-cascode amplifier bias techniques | Wenjun Su, Chiewcharn Narathong, Aristotele Hadjichristos | 2014-07-15 |
| 8750338 | Symmetrical clock distribution in multi-stage high speed data conversion circuits | Bo Zhang, Mohammad Nejad, Jun Cao | 2014-06-10 |
| 8259762 | Symmetrical clock distribution in multi-stage high speed data conversion circuits | Bo Zhang, Mohammad Nejad, Jun Cao | 2012-09-04 |
| 7974337 | High speed receive equalizer architecture | Afshin Momtaz, Mario Caresosa, David Chung, Davide Tonietto, Bruce J. Currivan +2 more | 2011-07-05 |
| 7864909 | Signal delay structure in high speed bit stream demultiplexer | Jun Cao | 2011-01-04 |
| 7834790 | Communication device including a power reduction mechanism | — | 2010-11-16 |
| 7778288 | Symmetrical clock distribution in multi-stage high speed data conversion circuits | Bo Zhang, Mohammad Nejad, Jun Cao | 2010-08-17 |
| 7623600 | High speed receive equalizer architecture | Afshin Momtaz, Mario Caresosa, David Chung, Davide Tonietto, Bruce J. Currivan +2 more | 2009-11-24 |
| 7616725 | Signal delay structure in high speed bit stream demultiplexer | Jun Cao | 2009-11-10 |
| 7577171 | Source centered clock supporting quad 10 GBPS serial interface | Mohammad Nejad, Ali Ghiasi | 2009-08-18 |
| 7511582 | Voltage controlled oscillator for use in phase locked loop | — | 2009-03-31 |
| 7449964 | System and method for tuning output drivers using voltage controlled oscillator capacitor settings | Bo Zhang, Ichiro Fujimori | 2008-11-11 |
| 7386084 | Method and system for pattern-independent phase adjustment in a clock and data recovery (CDR) circuit | — | 2008-06-10 |
| 7346082 | High-speed serial bit stream multiplexing and demultiplexing integrated circuits | Ali Ghiasi, Mohammad Nejad | 2008-03-18 |
| 7319706 | Symmetrical clock distribution in multi-stage high speed data conversion circuits | Bo Zhang, Mohammad Nejad, Jun Cao | 2008-01-15 |
| 7319351 | Delay generator with symmetric signal paths | Bo Zhang | 2008-01-15 |
| 7289543 | System and method for testing the operation of a DLL-based interface | Bo Zhang | 2007-10-30 |
| 7262659 | Adaptable voltage control for a variable gain amplifier | Mario Caresosa | 2007-08-28 |
| 7142013 | One-level zero-current-state exclusive or (XOR) gate | — | 2006-11-28 |
| 7135926 | Adaptable voltage control for a variable gain amplifier | Mario Caresosa | 2006-11-14 |
| 7109799 | Current-controlled CMOS wideband data amplifier circuits | Jun Cao | 2006-09-19 |
| 7098692 | Switchable power domains for 1.2v and 3.3v pad voltages | Sridevi R. Joshi, Mohammad Nejad, Daniel Schoch | 2006-08-29 |