Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6041418 | Race free and technology independent flag generating circuitry associated with two asynchronous clocks | Feng Chen, Le T. Ly, Jiancheng Mo, Hosahalli R. Srinivas | 2000-03-21 |
| 6031887 | High-speed binary synchronous counter | Santosh K. Misra, Jiancheng Mo, Hosahalli R. Srinivas | 2000-02-29 |
| 6018758 | Squarer with diagonal row merged into folded partial product array | William R. Griesbach | 2000-01-25 |
| 5983333 | High speed module address generator | Mohit Kishore Prasad | 1999-11-09 |
| 5977864 | High speed comparator with bit-wise masking | Michael S. Buonpane, Jiancheng Mo | 1999-11-02 |
| 5978826 | Adder with even/odd 1-bit adder cells | — | 1999-11-02 |
| 5958036 | Circuit for arbitrating interrupts with programmable priority levels | Geoffrey Francis Burns, Douglas J. Rhodes, Marck E. Thierbach | 1999-09-28 |
| 5946369 | High-speed binary synchronous counter with precomputation of carry-independent terms | Santosh K. Misra, Jiancheng Mo, Hosahalli R. Srinivas | 1999-08-31 |
| 5928317 | Fast converter for left-to-right carry-free multiplier | Jalil Fadavi-Ardekani, Hosahalli R. Srinivas | 1999-07-27 |
| 5925143 | Scan-bypass architecture without additional external latches | Pamela S. Gillis, Dennis A. Miller, Maria Noack, Steven F. Oakland, Chris J. Rebeor +2 more | 1999-07-20 |
| 5883825 | Reduction of partial product arrays using pre-propagate set-up | — | 1999-03-16 |
| 5719879 | Scan-bypass architecture without additional external latches | Pamela S. Gillis, Dennis A. Miller, Maria Noack, Steven F. Oakland, Chris J. Rebeor +2 more | 1998-02-17 |