Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11704467 | Automated balanced global clock tree synthesis in multi level physical hierarchy | Ashima Sahil Dabare, Anusha Reddy Sindhwala, Prakasha Karkada Holla, Sivakumar Arulanantham, Srinivasan Krishnamurthy +2 more | 2023-07-18 |
| 8863058 | Characterization based buffering and sizing for system performance optimization | Anup Nagrath | 2014-10-14 |
| 8839171 | Method of global design closure at top level and driving of downstream implementation flow | Ravi Varadarajan, Jitendra Gupta, Priyank Mittal, Kaushal Kishore Pathak, Kshitiz Krishna +2 more | 2014-09-16 |
| 8782582 | Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis | Jitendra Gupta, Ashima Sahil Dabare, Kshitiz Krishna, Ravi Varadarajan | 2014-07-15 |