Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11704467 | Automated balanced global clock tree synthesis in multi level physical hierarchy | Sanjiv Mathur, Anusha Reddy Sindhwala, Prakasha Karkada Holla, Sivakumar Arulanantham, Srinivasan Krishnamurthy +2 more | 2023-07-18 |
| 8782582 | Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis | Jitendra Gupta, Kshitiz Krishna, Sanjiv Mathur, Ravi Varadarajan | 2014-07-15 |