SA

Sivakumar Arulanantham

SY Synopsys: 2 patents #669 of 2,302Top 30%
Overall (All Time): #1,750,348 of 4,157,543Top 45%
2
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11914939 Clock re-convergence pessimism removal through pin sharing during clock tree planning Prashant Gupta, Shibaji Banerjee 2024-02-27
11704467 Automated balanced global clock tree synthesis in multi level physical hierarchy Ashima Sahil Dabare, Sanjiv Mathur, Anusha Reddy Sindhwala, Prakasha Karkada Holla, Srinivasan Krishnamurthy +2 more 2023-07-18