Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8839171 | Method of global design closure at top level and driving of downstream implementation flow | Jitendra Gupta, Sanjiv Mathur, Priyank Mittal, Kaushal Kishore Pathak, Kshitiz Krishna +2 more | 2014-09-16 |
| 8782582 | Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis | Jitendra Gupta, Ashima Sahil Dabare, Kshitiz Krishna, Sanjiv Mathur | 2014-07-15 |
| 8732647 | Method for creating physical connections in 3D integrated circuits | Lenuta Georgeta Claudia Rusu, Kaushal Kishore Pathak | 2014-05-20 |
| 7451427 | Bus representation for efficient physical synthesis of integrated circuit designs | — | 2008-11-11 |
| 5838583 | Optimized placement and routing of datapaths | Robert Thompson | 1998-11-17 |
| 5604680 | Virtual interface representation of hierarchical symbolic layouts | Cyrus Bamji | 1997-02-18 |
| 5581474 | Identifying overconstraints using port abstraction graphs | Cyrus Bamji | 1996-12-03 |
| 5568396 | Identifying overconstraints using port abstraction graphs | Cyrus Bamji | 1996-10-22 |
| 5381343 | Hier archical pitchmaking compaction method and system for integrated circuit design | Cyrus Bamji | 1995-01-10 |
| 5281558 | Cloning method and system for hierarchical compaction | Cyrus Bamji | 1994-01-25 |