Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12323164 | Capacity-expanding memory control component | Enrique Musoll, Anh T. Tran, Chi Feng | 2025-06-03 |
| 12277002 | Low-latency retimer with seamless clock switchover | Jitendra Mohan, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal +4 more | 2025-04-15 |
| 12143288 | Low-latency signaling-link retimer | Casey Morrison, Enrique Musoll, Jitendra Mohan, Pulkit Khandelwal, Vikas Khandelwal +4 more | 2024-11-12 |
| 12095480 | Capacity-expanding memory control component | Enrique Musoll, Anh T. Tran, Chi Feng | 2024-09-17 |
| 12061793 | Capacity-expanding memory control component | Enrique Musoll, Anh T. Tran, Chi Feng | 2024-08-13 |
| 12032479 | Metadata-caching integrated circuit device | Enrique Musoll, Anh T. Tran | 2024-07-09 |
| 12003610 | Retimer with mesochronous intra-lane path controllers | Enrique Musoll, Casey Morrison, Ken (Keqin) Han, Pulkit Khandelwal | 2024-06-04 |
| 11949629 | Retimer with path-coordinated flow-rate compensation | Enrique Musoll, Ken (Keqin) Han, Pulkit Khandelwal, Casey Morrison | 2024-04-02 |
| 11853115 | Low-latency retimer with seamless clock switchover | Jitendra Mohan, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal +4 more | 2023-12-26 |
| 11722152 | Capacity-expanding memory control component | Enrique Musoll, Anh T. Tran, Chi Feng | 2023-08-08 |
| 11487317 | Low-latency retimer with seamless clock switchover | Jitendra Mohan, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal +4 more | 2022-11-01 |
| 11424905 | Retimer with mesochronous intra-lane path controllers | Enrique Musoll, Casey Morrison, Ken (Keqin) Han, Pulkit Khandelwal | 2022-08-23 |
| 11349626 | Retimer with path-coordinated flow-rate compensation | Enrique Musoll, Ken (Keqin) Han, Pulkit Khandelwal, Casey Morrison | 2022-05-31 |
| 11327913 | Configurable-aggregation retimer with media-dedicated controllers | Casey Morrison, Charan Enugala, Chi Feng, Enrique Musoll, Jitendra Mohan +4 more | 2022-05-10 |
| 11258696 | Low-latency signaling-link retimer | Casey Morrison, Enrique Musoll, Jitendra Mohan, Pulkit Khandelwal, Vikas Khandelwal +4 more | 2022-02-22 |
| 11150687 | Low-latency retimer with seamless clock switchover | Jitendra Mohan, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal +4 more | 2021-10-19 |
| 9705808 | Flow aware buffer management for data center switches | Peter Newman | 2017-07-11 |
| 9337120 | Multi-chip module with multiple interposers | Li Li, Lin Shen | 2016-05-10 |
| 8972611 | Multi-server consolidated input/output (IO) device | Michael B. Galles | 2015-03-03 |
| 8565092 | Dynamic flow redistribution for head of line blocking avoidance | Prakash Appanna | 2013-10-22 |
| 8249069 | Forwarding multi-destination packets in a network with virtual port channels | Pirabhu Raman, Dinesh G. Dutt, Mahesh Maddury, Vijay Rangarajan, Ray Kloth +1 more | 2012-08-21 |