Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Casey Morrison — 17 Patents

ALAstera Labs: 12 patents #4 of 21Top 20%
TITexas Instruments: 3 patents #4,069 of 12,488Top 35%
San Jose, CA: #3,861 of 32,062 inventorsTop 15%
California: #35,467 of 386,348 inventorsTop 10%
Overall (All Time): #263,971 of 4,157,543Top 7%
17 Patents All Time
Casey Morrison has been granted 17 US patents while listed as an inventor at Astera Labs. The first was granted in 2020 and the most recent in December 2025. Casey Morrison ranks #263,971 of 4,157,543 US inventors in our database (top 6.3%). Patent records list Casey Morrison in San Jose, CA, US.

Issued Patents All Time

Showing 1–17 of 17 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12489590 Retimer with path-coordinated flow-rate compensation Enrique Musoll, Subbarao Arumilli, Ken (Keqin) Han, Pulkit Khandelwal 2025-12-02
12327135 Retimer with host-interactive data logging engine Ken (Keqin) Han, Charan Enugala, Pulkit Khandelwal, Vikas Khandelwal 2025-06-10
12277002 Low-latency retimer with seamless clock switchover Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han +4 more 2025-04-15
12143288 Low-latency signaling-link retimer Enrique Musoll, Jitendra Mohan, Pulkit Khandelwal, Subbarao Arumilli, Vikas Khandelwal +4 more 2024-11-12 $156,244,000
12003610 Retimer with mesochronous intra-lane path controllers Enrique Musoll, Ken (Keqin) Han, Pulkit Khandelwal, Subbarao Arumilli 2024-06-04 $105,677,000
11949629 Retimer with path-coordinated flow-rate compensation Enrique Musoll, Subbarao Arumilli, Ken (Keqin) Han, Pulkit Khandelwal 2024-04-02
11941436 Retimer with host-interactive data logging engine Ken (Keqin) Han, Charan Enugala, Pulkit Khandelwal, Vikas Khandelwal 2024-03-26
11853115 Low-latency retimer with seamless clock switchover Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han +4 more 2023-12-26
11487317 Low-latency retimer with seamless clock switchover Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han +4 more 2022-11-01
11424905 Retimer with mesochronous intra-lane path controllers Enrique Musoll, Ken (Keqin) Han, Pulkit Khandelwal, Subbarao Arumilli 2022-08-23
11349626 Retimer with path-coordinated flow-rate compensation Enrique Musoll, Subbarao Arumilli, Ken (Keqin) Han, Pulkit Khandelwal 2022-05-31
11327913 Configurable-aggregation retimer with media-dedicated controllers Charan Enugala, Chi Feng, Enrique Musoll, Jitendra Mohan, Ken (Keqin) Han +4 more 2022-05-10
11258696 Low-latency signaling-link retimer Enrique Musoll, Jitendra Mohan, Pulkit Khandelwal, Subbarao Arumilli, Vikas Khandelwal +4 more 2022-02-22
11211315 Semiconductor package with terminal pattern for increased channel density Lee Martin Sledjeski 2021-12-28 $39,584,000
11151066 Link width scaling across multiple retimer devices Pakyiu Leung 2021-10-19 $43,571,000
11150687 Low-latency retimer with seamless clock switchover Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han +4 more 2021-10-19
10671553 Link width scaling across multiple retimer devices Pakyiu Leung 2020-06-02 $33,342,000