Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6658502 | Multi-channel and multi-modal direct memory access controller for optimizing performance of host bus | Franklyn H. Story | 2003-12-02 |
| 6578098 | Predictive mechanism for ASB slave responses | James J. Jirgal | 2003-06-10 |
| 6560663 | Method and system for controlling internal busses to prevent bus contention during internal scan testing | Brian Logsdon, Franklyn H. Story, Ken Jaramillo | 2003-05-06 |
| 6523075 | Method and system for controlling internal busses to prevent busses contention during internal scan testing by using a centralized control resource | Ken Jaramillo, Brian Logsdon, Franklyn H. Story | 2003-02-18 |
| 6519670 | Method and system for optimizing a host bus that directly interfaces to a 16-bit PCMCIA host bus adapter | — | 2003-02-11 |
| 6311248 | Method and system for optimized data transfers in a mixed 64-bit/32-bit PCI environment | Peter Chambers | 2001-10-30 |
| 6301631 | Memory mapping method for eliminating dual address cycles in a peripheral component interconnect environment | Peter Chambers, Swaroop Adusumilli | 2001-10-09 |
| 6289406 | Optimizing the performance of asynchronous bus bridges with dynamic transactions | Peter Chambers, Swaroop Adusumilli | 2001-09-11 |
| 6233632 | Optimizing peripheral component interconnect transactions in a mixed 32/64-bit environment by eliminating unnecessary data transfers | Peter Chambers | 2001-05-15 |
| 6230216 | Method for eliminating dual address cycles in a peripheral component interconnect environment | Peter Chambers, Swaroop Adusumilli | 2001-05-08 |
| 6223232 | System and method to predict configuration of a bus target | Swaroop Adusumilli | 2001-04-24 |
| 6178478 | Smart target mechanism for eliminating dual address cycles in a peripheral component interconnect environment | Peter Chambers, Swaroop Adusumilli | 2001-01-23 |