Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
RJ

Robert E. Jeter — 51 Patents

Apple: 40 patents #741 of 18,612Top 4%
Cisco: 11 patents #1,278 of 13,007Top 10%
Santa Clara, CA: #203 of 9,301 inventorsTop 3%
California: #7,783 of 386,348 inventorsTop 3%
Overall (All Time): #51,932 of 4,157,543Top 2%
51 Patents All Time
Robert E. Jeter has been granted 51 US patents while listed as an inventor at Apple. The first was granted in 2006 and the most recent in October 2025. Robert E. Jeter ranks #51,932 of 4,157,543 US inventors in our database (top 1.2%). Patent records list Robert E. Jeter in Santa Clara, CA, US.

Patents per Year

Patents granted per year, 2006 to 2025Bar chart with a peak of 7 patents in 2016.peak 72006: 2 patents20062007: 5 patents2008: 1 patents20082011: 2 patents2013: 1 patents20132016: 7 patents2017: 6 patents20172018: 5 patents2019: 6 patents20192020: 2 patents2021: 1 patents20212022: 4 patents2023: 1 patents20232024: 3 patents2025: 5 patents2025

Issued Patents All Time

Showing 26–50 of 51 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9928890 System and method for calibrating memory using credit-based segmentation control Rakesh L. Notani, Kai Lun Hsiung, Alma L. Juarez Dominguez 2018-03-27 $64,288,000
9891853 Memory calibration abort Neeraj Parik, Gurjeet S. Saund, Rakesh L. Notani 2018-02-13 $82,592,000
9697145 Memory interface system Neeraj Parik 2017-07-04
9698797 Hierarchical feedback-controlled oscillator techniques Manu Gulati, Suhas Kumar Suvarna Ramesh, Venkata Ramana Malladi, Thomas H. Huang, Rakesh L. Notani +1 more 2017-07-04
9691470 Apparatus and method for restricted range memory calibration Rakesh L. Notani 2017-06-27 $77,923,000
9672882 Conditional reference voltage calibration of a memory system in data transmisson Rakesh L. Notani 2017-06-06 $75,498,000
9666264 Apparatus and method for memory calibration averaging Kai Lun Hsiung, Rakesh L. Notani, Xingchao C. Yuan 2017-05-30 $83,886,000
9640244 Pre-calibration for multiple performance states Rakesh L. Notani 2017-05-02 $80,146,000
9477259 Calibration of clock signal for data transmission Neeraj Parik, Sukalpa Biswas 2016-10-25 $74,258,000
9436387 System and method for calibration of a memory interface 2016-09-06 $77,599,000
9396778 Conditional memory calibration cancellation Kai Lun Hsiung, Rakesh L. Notani 2016-07-19 $68,975,000
9390681 Temporal filtering for dynamic pixel and backlight control Ulrich T. Barnhoefer 2016-07-12 $81,101,000
9305622 Data strobe to data delay calibration 2016-04-05 $46,684,000
9286961 Memory controller half-clock delay adjustment Rakesh L. Notani, Kiran B. Kattel 2016-03-15 $68,647,000
9236029 Histogram generation and evaluation for dynamic pixel and backlight control Ulrich T. Barnhoefer 2016-01-12 $83,071,000
8453147 Techniques for reducing thread overhead for systems with multiple multi-threaded processors John Marshall, William Lee, Trevor Garner 2013-05-28 $42,653,000
8041929 Techniques for hardware-assisted multi-threaded processing Trevor Gamer, William Lee, Scott C. Smith, Gegory Goss 2011-10-18 $22,947,000
8010966 Multi-threaded processing using path locks Trevor Garner, John Marshall, Aaron T. Kirk 2011-08-30 $40,737,000
7434016 Memory fence with background lock release 2008-10-07 $19,989,000
7290096 Full access to memory interfaces via remote request John Marshall, Jeffery B. Scott 2007-10-30 $49,332,000
7290105 Zero overhead resource locks with attributes Kenneth H. Potter, Jr., Darren Kerr, John Marshall, Manish Changela 2007-10-30 $49,332,000
7257681 Maintaining entity order with gate managers John Chanak 2007-08-14 $79,689,000
7254687 Memory controller that tracks queue operations to detect race conditions Kenneth H. Potter, Jr. 2007-08-07 $136,685,000
7194568 System and method for dynamic mirror-bank addressing Kenneth H. Potter, Jr. 2007-03-20 $75,178,000
7155588 Memory fence with background lock release 2006-12-26 $67,404,000