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Programmable arrayed processing engine architecture for a network switch |
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Barry Bruins |
2009-01-06 |
| 7380101 |
Architecture for a processor complex of an arrayed pipelined processing engine |
Michael L. Wright, Kenneth Michael Key, William E. Jennings |
2008-05-27 |
| 7292578 |
Flexible, high performance support for QoS on an arbitrary number of queues |
Van L. Jacobson |
2007-11-06 |
| 7290105 |
Zero overhead resource locks with attributes |
Robert E. Jeter, Kenneth H. Potter, Jr., John Marshall, Manish Changela |
2007-10-30 |
| 7260518 |
Network flow switching and flow data report |
Barry Bruins |
2007-08-21 |
| 7139899 |
Selected register decode values for pipeline stage register addressing |
John Marshall |
2006-11-21 |
| 7100021 |
Barrier synchronization mechanism for processors of a systolic array |
John Marshall, Barry S. Burns |
2006-08-29 |
| 6986022 |
Boundary synchronization mechanism for a processor of a systolic array |
John Marshall, Barry S. Burns |
2006-01-10 |
| 6965615 |
Packet striping across a parallel header processor |
Jeffery B. Scott, John Marshall, Scott Nellenbach |
2005-11-15 |
| 6920562 |
Tightly coupled software protocol decode with hardware data encryption |
John Marshall |
2005-07-19 |
| 6889181 |
Network flow switching and flow data export |
Barry Bruins |
2005-05-03 |
| 6836838 |
Architecture for a processor complex of an arrayed pipelined processing engine |
Michael L. Wright, Kenneth Michael Key, William E. Jennings |
2004-12-28 |
| 6804815 |
Sequence control mechanism for enabling out of order context processing |
Jeffery B. Scott, John Marshall, Kenneth H. Potter, Jr., Scott Nellenbach |
2004-10-12 |
| 6590894 |
Network flow switching and flow data export |
Barry Bruins |
2003-07-08 |
| 6513108 |
Programmable processing engine for efficiently processing transient data |
Kenneth Michael Key, Michael L. Wright, William E. Jennings |
2003-01-28 |
| 6442669 |
Architecture for a process complex of an arrayed pipelined processing engine |
Michael L. Wright, Kenneth Michael Key, William E. Jennings |
2002-08-27 |
| 6308148 |
Network flow data export |
Barry Bruins |
2001-10-23 |
| 6272621 |
Synchronization and control system for an arrayed processing engine |
Kenneth Michael Key, Michael L. Wright, William E. Jennings |
2001-08-07 |
| 6243667 |
Network flow switching and flow data export |
Barry Bruins |
2001-06-05 |
| 6195739 |
Method and apparatus for passing data among processor complex stages of a pipelined processing engine |
Michael L. Wright, Kenneth Michael Key, William E. Jennings |
2001-02-27 |
| 6173386 |
Parallel processor with debug capability |
Kenneth Michael Key, Michael L. Wright, William E. Jennings, Scott Nellenbach |
2001-01-09 |
| 6119215 |
Synchronization and control system for an arrayed processing engine |
Kenneth Michael Key, Michael L. Wright, William E. Jennings |
2000-09-12 |
| 6101599 |
System for context switching between processing elements in a pipeline of processing elements |
Michael L. Wright, Kenneth Michael Key, William E. Jennings |
2000-08-08 |