Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7505887 | Building a simulation of design block using a bus functional model and an HDL testbench | Jorge Ernesto Carrillo, Lester S. Sanders, Yong-Guang Zhu | 2009-03-17 |
| 6487708 | Hierarchical location constraints for programmable layouts | — | 2002-11-26 |
| 5418473 | Single event upset immune logic family | — | 1995-05-23 |
| 5406513 | Mechanism for preventing radiation induced latch-up in CMOS integrated circuits | Sterling Whitaker, Kelly Cameron | 1995-04-11 |