Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11626403 | Self restoring logic structures | Gary Maki | 2023-04-11 |
| 11552079 | Self restoring logic structures | Gary Maki | 2023-01-10 |
| 11069683 | Self restoring logic structures | Gary Maki | 2021-07-20 |
| 8081010 | Self restoring logic | Gary Maki, Lowell H. Miles | 2011-12-20 |
| 7624368 | Optimization of digital designs | Lowell H. Miles | 2009-11-24 |
| 7576562 | Diagnosable structured logic array | Lowell H. Miles, Jody W. Gambles, Gary Maki | 2009-08-18 |
| 7543212 | Low-density parity-check (LDPC) encoder | Lowell H. Miles | 2009-06-02 |
| 7489538 | Radiation tolerant combinational logic cell | Gary Maki, Jody W. Gambles | 2009-02-10 |
| 6993731 | Optimization of digital designs | Lowell H. Miles | 2006-01-31 |
| 6892373 | Integrated circuit cell library | Lowell H. Miles | 2005-05-10 |
| 6792589 | Digital design using selection operations | Lowell H. Miles, Eric Cameron | 2004-09-14 |
| 6779156 | Digital circuits using universal logic gates | Lowell H. Miles, Eric Cameron, Gregory Donohoe, Jody W. Gambles | 2004-08-17 |
| 6779158 | Digital logic optimization using selection operators | Lowell H. Miles, Eric Cameron, Jody W. Gambles | 2004-08-17 |
| 6434037 | MUX-based ROM using n-bit subfunction encoding | — | 2002-08-13 |
| 5406513 | Mechanism for preventing radiation induced latch-up in CMOS integrated circuits | John A. Canaris, Kelly Cameron | 1995-04-11 |
| 5111429 | Single event upset hardening CMOS memory circuit | — | 1992-05-05 |
| 4912348 | Method for designing pass transistor asynchronous sequential circuits | Gary Maki | 1990-03-27 |
| 4622648 | Combinational logic structure using PASS transistors | — | 1986-11-11 |
| 4566064 | Combinational logic structure using PASS transistors | — | 1986-01-21 |
| 4541067 | Combinational logic structure using PASS transistors | — | 1985-09-10 |