Issued Patents All Time
Showing 51–75 of 178 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9477605 | Memory hierarchy using row-based compression | Gabriel H. Loh | 2016-10-25 |
| 9477526 | Cache utilization and eviction based on allocated priority tokens | Daniel R. Johnson, Minsoo Rhu, Stephen W. Keckler | 2016-10-25 |
| 9454419 | Partitionable data bus | Gabriel H. Loh, Yi Xu | 2016-09-27 |
| 9436398 | Memory interface supporting both ECC and per-byte data masking | Warren Fritz Kruger | 2016-09-06 |
| 9406403 | Spare memory external to protected memory | Gabriel H. Loh, Vilas Sridharan | 2016-08-02 |
| 9367455 | Using predictions for store-to-load forwarding | Yasuko Eckert, Lena E. Olson, Srilatha Manne | 2016-06-14 |
| 9354892 | Creating SIMD efficient code by transferring register state through common memory | Timothy G. Rogers, Bradford M. Beckmann | 2016-05-31 |
| 9317296 | High level software execution mask override | Timothy G. Rogers, Bradford M. Beckmann | 2016-04-19 |
| 9298615 | Methods and apparatus for soft-partitioning of a data cache for stack data | Lena E. Olson, Yasuko Eckert, Vilas Sridharan, Mark D. Hill, Srilatha Manne | 2016-03-29 |
| 9286948 | Query operations for stacked-die memory device | Gabriel H. Loh, Nuwan Jayasena, Yasuko Eckert | 2016-03-15 |
| 9251069 | Mechanisms to bound the presence of cache blocks with specific properties in caches | Yasuko Eckert, Gabriel H. Loh, Mauricio Breternitz, Srilatha Manne, Nuwan Jayasena +1 more | 2016-02-02 |
| 9244629 | Method and system for asymmetrical processing with managed data affinity | Lisa R. Hsu, Gabriel H. Loh, Nuwan Jayasena | 2016-01-26 |
| 9235528 | Write endurance management techniques in the logic layer of a stacked memory | Lisa R. Hsu, Gabriel H. Loh, Michael Ignatowski, Michael Schulte, Nuwan Jayasena | 2016-01-12 |
| 9229803 | Dirty cacheline duplication | Gabriel H. Loh, Vilas Sridharan, Jaewoong Sim | 2016-01-05 |
| 9218204 | Processing engine for complex atomic operations | Michael Schulte, Nuwan Jayasena, Gabriel H. Loh | 2015-12-22 |
| 9183055 | Selecting a resource from a set of resources for performing an operation | Bradford M. Beckmann, Mithuna S. Thottethodi, Mauricio Breternitz, Lisa R. Hsu, Gabriel H. Loh +1 more | 2015-11-10 |
| 9135185 | Die-stacked memory device providing data translation | Gabriel H. Loh, Bradford M. Beckmann, Michael Ignatowski, Michael Schulte, Lisa R. Hsu +1 more | 2015-09-15 |
| 9106260 | Parity data management for a memory architecture | Vilas Sridharan, Gabriel H. Loh | 2015-08-11 |
| 9075730 | Mechanisms to bound the presence of cache blocks with specific properties in caches | Mithuna S. Thottethodi, Gabriel H. Loh, Yasuko Eckert, Bradford M. Beckmann | 2015-07-07 |
| 9064606 | Memory interface supporting both ECC and per-byte data masking | Warren Fritz Kruger | 2015-06-23 |
| 9065651 | Apparatus and method for automatic repeat request with reduced resource allocation overhead in a wireless VoIP communication system | Jack Anthony Smith, Hao Bi, Sean Michael McBeath, Danny T. Pinckley, John D. Reed | 2015-06-23 |
| 9021207 | Management of cache size | John Kalamatianos, Edward J. McLellan, Paul Keltcher, Srilatha Manne, Richard E. Klass | 2015-04-28 |
| 9011204 | Reducing small colloidal particle concentrations in feed and/or byproduct fluids in the context of waterjet processing | Chidambaram Raghavan, Tanner Coker, Scott Thomas, John H. Olsen | 2015-04-21 |
| 9003130 | Multi-core processing device with invalidation cache tags and methods | Bradford M. Beckmann | 2015-04-07 |
| 8949544 | Bypassing a cache when handling memory requests | Gabriel H. Loh, Jaewoong Sim | 2015-02-03 |