Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7328384 | Method and apparatus using device defects as an identifier | Chidamber R. Kulkarni, Stephen M. Trimberger | 2008-02-05 |
| 6882182 | Tunable clock distribution system for reducing power dissipation | Robert O. Conn, Christopher H. Kingsley, Austin H. Lesea | 2005-04-19 |
| 6381732 | FPGA customizable to accept selected macros | James L. Burnham, Joseph D. Linoff | 2002-04-30 |
| 6357037 | Methods to securely configure an FPGA to accept selected macros | James L. Burnham, Joseph D. Linoff | 2002-03-12 |
| 6324676 | FPGA customizable to accept selected macros | James L. Burnham, Joseph D. Linoff | 2001-11-27 |
| 6324672 | Method for configuring circuits over a data communications link | Joseph D. Linoff, Robert W. Wells | 2001-11-27 |
| 6301695 | Methods to securely configure an FPGA using macro markers | James L. Burnham | 2001-10-09 |
| 6172520 | FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA | Bernard J. New | 2001-01-09 |
| 6118938 | Memory map computer control system for programmable ICS | Joseph D. Linoff, Stephen L. Wasson | 2000-09-12 |
| 6107821 | On-chip logic analysis and method for using the same | Steven Hennick Kelem | 2000-08-22 |
| 6049222 | Configuring an FPGA using embedded memory | — | 2000-04-11 |
| 6044025 | PROM with built-in JTAG capability for configuring FPGAs | — | 2000-03-28 |
| 6028445 | Decoder structure and method for FPGA configuration | — | 2000-02-22 |
| 6023565 | Method for configuring circuits over a data communications link | Joseph D. Linoff, Robert W. Wells | 2000-02-08 |
| 5949690 | Schematic design entry with annotated timing | — | 1999-09-07 |
| 5946478 | Method for generating a secure macro element of a design for a programmable IC | — | 1999-08-31 |
| 5928338 | Method for providing temporary registers in a local bus device by reusing configuration bits otherwise unused after system reset | — | 1999-07-27 |
| 5870309 | HDL design entry with annotated timing | — | 1999-02-09 |
| 5673198 | Concurrent electronic circuit design and implementation | Robert W. Wells | 1997-09-30 |