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Tunable clock distribution system for reducing power dissipation |
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FPGA customizable to accept selected macros |
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2002-04-30 |
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Methods to securely configure an FPGA to accept selected macros |
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FPGA customizable to accept selected macros |
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2001-11-27 |
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Method for configuring circuits over a data communications link |
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2001-11-27 |
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Methods to securely configure an FPGA using macro markers |
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Memory map computer control system for programmable ICS |
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On-chip logic analysis and method for using the same |
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2000-08-22 |
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Configuring an FPGA using embedded memory |
— |
2000-04-11 |
| 6044025 |
PROM with built-in JTAG capability for configuring FPGAs |
— |
2000-03-28 |
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Decoder structure and method for FPGA configuration |
— |
2000-02-22 |
| 6023565 |
Method for configuring circuits over a data communications link |
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2000-02-08 |
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Schematic design entry with annotated timing |
— |
1999-09-07 |
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Method for generating a secure macro element of a design for a programmable IC |
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1999-08-31 |
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Method for providing temporary registers in a local bus device by reusing configuration bits otherwise unused after system reset |
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1999-07-27 |
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HDL design entry with annotated timing |
— |
1999-02-09 |
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Concurrent electronic circuit design and implementation |
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