Issued Patents All Time
Showing 26–39 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5764556 | Method and apparatus for performing floating point addition | — | 1998-06-09 |
| 5748932 | Cache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequence | Korbin S. Van Dyke, John G. Favor | 1998-05-05 |
| 5682492 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | Harold L. McFarland, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1997-10-28 |
| 5649137 | Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency | John G. Favor, Korbin S. Van Dyke | 1997-07-15 |
| 5515518 | Two-level branch prediction cache | John G. Favor, Korbin S. Van Dyke | 1996-05-07 |
| 5513330 | Apparatus for superscalar instruction predecoding using cached instruction lengths | — | 1996-04-30 |
| 5511175 | Method an apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency | John G. Favor, Korbin S. Van Dyke | 1996-04-23 |
| 5442757 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | Harold L. McFarland, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1995-08-15 |
| 5327547 | Two-level branch prediction cache | John G. Favor, Korbin S. Van Dyke | 1994-07-05 |
| 5230068 | Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence | Korbin S. Van Dyke, John G. Favor | 1993-07-20 |
| 5226130 | Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency | John G. Favor, Korbin S. Van Dyke | 1993-07-06 |
| 5226126 | Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags | Harold L. McFarland, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1993-07-06 |
| 5163140 | Two-level branch prediction cache | John G. Favor, Korbin S. Van Dyke | 1992-11-10 |
| 5093778 | Integrated single structure branch prediction cache | John G. Favor, Korbin S. Van Dyke, Walstein Bennett Smith, III | 1992-03-03 |