Issued Patents All Time
Showing 126–150 of 198 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10908987 | Handling memory errors in computing systems | Amit Pandey | 2021-02-02 |
| 10901492 | Power reduction in processor pipeline by detecting zeros | Nafea Bshara, Randy Renfu Huang, Ali Ghassan Saidi | 2021-01-26 |
| 10896001 | Notifications in integrated circuits | Thomas A. Volpe, Nafea Bshara, Raymond Scott Whiteside | 2021-01-19 |
| 10884707 | Transpose operations using processing element array | Haichen Li, Jeffrey T. Huynh, Yu Zhou, Se-Jong Oh | 2021-01-05 |
| 10877552 | Dynamic power reduction through data transfer request limiting | Sundeep Amirineni, Akshay Balasubramanian | 2020-12-29 |
| 10846201 | Performance debug for networks | Jindrich Zejda, Drazen Borkovic, Thomas A. Volpe | 2020-11-24 |
| 10846621 | Fast context switching for computational networks | Randy Renfu Huang, Jindrich Zejda, Drazen Borkovic | 2020-11-24 |
| 10831693 | Multicast master | Randy Renfu Huang | 2020-11-10 |
| 10817260 | Reducing dynamic power consumption in arrays | Randy Renfu Huang, Thomas Elmer, Sundeep Amirineni, Thomas A. Volpe | 2020-10-27 |
| 10803379 | Multi-memory on-chip computational network | Randy Renfu Huang | 2020-10-13 |
| 10803007 | Reconfigurable instruction | Thomas A. Volpe, Nafea Bshara, Raymond Scott Whiteside | 2020-10-13 |
| 10768856 | Memory access for multiple circuit components | Sundeep Amirineni, Akshay Balasubramanian, Eyal Freund | 2020-09-08 |
| 10761822 | Synchronization of computation engines with non-blocking instructions | Drazen Borkovic, Jindrich Zejda, Taemin Kim | 2020-09-01 |
| 10761939 | Powering-down or rebooting a device in a system fabric | Kun Xu, Thomas A. Volpe, Mark Anthony Banse | 2020-09-01 |
| 10746792 | Debug mechanisms for a processor circuit | Gil Stoler, Nafea Bshara | 2020-08-18 |
| 10747700 | Dynamically configurable pipeline | Adiel Sarusi, Ori Weber, Erez Izenberg | 2020-08-18 |
| 10740265 | PCI-based bus system having peripheral device address translation based on base address register (BAR) index | Kun Xu | 2020-08-11 |
| 10740432 | Hardware implementation of mathematical functions | Randy Renfu Huang, Mohammad El-Shabani, Sundeep Amirineni, Kenneth Wayne Patton, Willis Wang | 2020-08-11 |
| 10742555 | Network congestion detection and resolution | Leah Shalev, Erez Izenberg, Nafea Bshara | 2020-08-11 |
| 10733498 | Parametric mathematical function approximation in integrated circuits | Sundeep Amirineni, Mohammad El-Shabani | 2020-08-04 |
| 10708241 | Hardware security accelerator | Nafea Bshara, Leah Shalev, Erez Izenberg | 2020-07-07 |
| 10708246 | Extending cryptographic-key lifespan in network encryption protocols | Noa Yehezkel, Ahmad Erew, Jonathan Cohen, Michael Baranchik | 2020-07-07 |
| 10691850 | Power projection using machine learning | Lev Makovsky, Adi Habusha | 2020-06-23 |
| 10678479 | Registers for restricted memory | Randy Renfu Huang, Sundeep Amirineni, Jeffrey T. Huynh | 2020-06-09 |
| 10678721 | Communication link testing | Christopher James BeSerra, Alex Levin | 2020-06-09 |