Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7863923 | Adaptive test time reduction for wafer-level testing | — | 2011-01-04 |
| 7626412 | Adaptive test time reduction for wafer-level testing | — | 2009-12-01 |
| 6941498 | Technique for debugging an integrated circuit having a parallel scan-chain architecture | Ismed D. S. Hartano, John Stephen Walther | 2005-09-06 |
| 6751768 | Hierarchical creation of vectors for quiescent current (IDDQ) tests for system-on-chip circuits | Neal C. Jaarsma, Chinsong Sul, Garrett O'Brien | 2004-06-15 |
| 6714036 | Monitor circuitry and method for testing analog and/or mixed signal integrated circuits | Joan Figueras | 2004-03-30 |
| 6587981 | Integrated circuit with scan test structure | Neal C. Jaarsma | 2003-07-01 |
| 6191603 | Modular embedded test system for use in integrated circuits | Robert Campbell Aitken | 2001-02-20 |
| 5323400 | Scan cell for weighted random pattern generation and method for its operation | Vinod K. Agarwal, Benoit Nadeau-Dostie | 1994-06-21 |