Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9766966 | Method and apparatus for on-chip adjustment of chip characteristics | — | 2017-09-19 |
| 9443733 | Method and apparatus for authenticating a semiconductor die | Patrick A. McKinley, Walter Lee McNall, Robert W. Shreeve, Thomas Page Bruch | 2016-09-13 |
| 8159241 | Method and apparatus for on-chip adjustment of chip characteristics | — | 2012-04-17 |
| 6751768 | Hierarchical creation of vectors for quiescent current (IDDQ) tests for system-on-chip circuits | Fidel Muradali, Chinsong Sul, Garrett O'Brien | 2004-06-15 |
| 6587981 | Integrated circuit with scan test structure | Fidel Muradali | 2003-07-01 |
| 5130989 | Serial and parallel scan technique for improved testing of systolic arrays | Daryl E. Anderson, Ralph H. Lanham | 1992-07-14 |