Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11144696 | Low cost design for test architecture | — | 2021-10-12 |
| 10712388 | Low cost design for test architecture | — | 2020-07-14 |
| 10338138 | Low cost design for test architecture | — | 2019-07-02 |
| 9231567 | Test solution for a random number generator | Hyukyong Kwon, Andy Ng | 2016-01-05 |
| 8924805 | Computer memory test structure | Sungjoon Kim | 2014-12-30 |
| 8841974 | Test solution for ring oscillators | Hyukyong Kwon, Andy Ng | 2014-09-23 |
| 8839058 | Multi-site testing of computer memory devices and serial IO ports | — | 2014-09-16 |
| 8667354 | Computer memory test structure | Sungjoon Kim | 2014-03-04 |
| 8598898 | Testing of high-speed input-output devices | Min-Kyu Kim, Son Nguyen | 2013-12-03 |
| 8543873 | Multi-site testing of computer memory devices and serial IO ports | — | 2013-09-24 |
| 8386867 | Computer memory test structure | Sungjoon Kim | 2013-02-26 |
| 8026726 | Fault testing for interconnections | Gijung Ahn | 2011-09-27 |
| 7984369 | Concurrent code checker and hardware efficient high-speed I/O having built-in self-test and debug features | Hoon Choi, Gijung Ahn | 2011-07-19 |
| 7840861 | Scan-based testing of devices implementing a test clock control structure (“TCCS”) | — | 2010-11-23 |
| 7831877 | Circuitry to prevent peak power problems during scan shift | Heon Cheol Kim | 2010-11-09 |
| 7793179 | Test clock control structures to generate configurable test clocks for scan-based testing of electronic circuits using programmable test clock controllers | — | 2010-09-07 |
| 7698088 | Interface test circuitry and methods | Heon Cheol Kim, Gijung Ahn | 2010-04-13 |
| 6751768 | Hierarchical creation of vectors for quiescent current (IDDQ) tests for system-on-chip circuits | Fidel Muradali, Neal C. Jaarsma, Garrett O'Brien | 2004-06-15 |