Issued Patents All Time
Showing 151–175 of 221 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7450798 | Automatic shutdown system and method for optical multiplexers and demultiplexers | Jun Su | 2008-11-11 |
| 7411287 | Staggered wirebonding configuration | — | 2008-08-12 |
| 7388272 | Chip package and producing method thereof | — | 2008-06-17 |
| 7355239 | Fabrication of semiconductor device exhibiting reduced dielectric loss in isolation trenches | Barbara Haselden | 2008-04-08 |
| 7326992 | Nonvolatile memory cell with multiple floating gates formed after the select gate | — | 2008-02-05 |
| 7312497 | Fabrication of conductive lines interconnecting first conductive gates in nonvolatile memories having second conductive gates provided by conductive gate lines, wherein the adjacent conductive gate lines for the adjacent columns are spaced from each other, and non-volatile memory structures | — | 2007-12-25 |
| 7301196 | Nonvolatile memories and methods of fabrication | — | 2007-11-27 |
| 7294883 | Nonvolatile memory cells with buried channel transistors | — | 2007-11-13 |
| 7291788 | Circuit substrate | Jia-Cheng Chen | 2007-11-06 |
| 7280717 | Automatic shutdown system and method for optical multiplexers and demultiplexers | Jun Su | 2007-10-09 |
| 7274063 | Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions | — | 2007-09-25 |
| 7238575 | Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures | — | 2007-07-03 |
| 7238983 | Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures | — | 2007-07-03 |
| 7230295 | Nonvolatile memory cell with multiple floating gates formed after the select gate | — | 2007-06-12 |
| 7221125 | System and method for charging a battery | — | 2007-05-22 |
| 7215841 | Extracting phase error in waveguides | Everett Wang, Sai Yu, Dmitri E. Nikonov | 2007-05-08 |
| 7214585 | Methods of fabricating integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges | — | 2007-05-08 |
| 7195964 | Fabrication of dielectric on a gate surface to insulate the gate from another element of an integrated circuit | — | 2007-03-27 |
| 7190019 | Integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges | — | 2007-03-13 |
| 7169667 | Nonvolatile memory cell with multiple floating gates formed after the select gate | — | 2007-01-30 |
| 7148104 | Fabrication of conductive lines interconnecting first conductive gates in nonvolatile memories having second conductive gates provided by conductive gate lines, wherein the adjacent conductive gate lines for the adjacent columns are spaced from each other, and non-volatile memory structures | — | 2006-12-12 |
| 7125745 | Multi-chip package substrate for flip-chip and wire bonding | Kun-Ching Chen, Po-Jen Cheng, Chih-Ming Chung, Yun-Hsiang Tien | 2006-10-24 |
| 7101757 | Nonvolatile memory cells with buried channel transistors | — | 2006-09-05 |
| 7091583 | Method and structure for prevention leakage of substrate strip | Ying-Chih Chen, Yun-Hsiang Tien, Ming-Jiun Lai | 2006-08-15 |
| 7091091 | Nonvolatile memory fabrication methods in which a dielectric layer underlying a floating gate layer is spaced from an edge of an isolation trench and/or an edge of the floating gate layer | — | 2006-08-15 |