Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5801417 | Self-aligned power MOSFET device with recessed gate and source | Dah W. Tsang, John W. Mosier, II, Theodore O. Meyer | 1998-09-01 |
| 5648283 | High density power device fabrication process using undercut oxide sidewalls | Dah W. Tsang, Dumitru Sdrulla, Theodore O. Meyer, John W. Mosier, II | 1997-07-15 |
| 5528058 | IGBT device with platinum lifetime control and reduced gaw | Dah W. Tsang, James M. Katana, Dumitru Sdrulla | 1996-06-18 |
| 5283201 | High density power device fabrication process | Dah W. Tsang, John W. Mosier, II, Theodore O. Meyer | 1994-02-01 |
| 5283202 | IGBT device with platinum lifetime control having gradient or profile tailored platinum diffusion regions | Dah W. Tsang, James M. Katana, Dumitra Scrulla | 1994-02-01 |
| 5262336 | IGBT process to produce platinum lifetime control | Dah W. Tsang, James M. Katana | 1993-11-16 |
| 5045903 | Topographic pattern delineated power MOSFET with profile tailored recessed source | Theodore O. Meyer, John W. Mosier, II, Theodore G. Hollinger, Dah W. Tsang | 1991-09-03 |
| 5019522 | Method of making topographic pattern delineated power MOSFET with profile tailored recessed source | Theodore O. Meyer, John W. Mosier, II, Theodore G. Hollinger, Dah W. Tsang | 1991-05-28 |
| 4895810 | Iopographic pattern delineated power mosfet with profile tailored recessed source | Theodore O. Meyer, John W. Mosier, II, Theodore G. Hollinger | 1990-01-23 |
| 4789886 | Method and apparatus for insulating high voltage semiconductor structures | — | 1988-12-06 |