Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate | Richard K. Williams, Wai Tien Chan | 2007-10-09 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate | Richard K. Williams, Wai Tien Chan | 2007-10-02 |
| 7265434 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology | Richard K. Williams, Wai Tien Chan | 2007-09-04 |
| 7211863 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology | Richard K. Williams, Wai Tien Chan | 2007-05-01 |
| 7202536 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology | Richard K. Williams, Wai Tien Chan | 2007-04-10 |
| 7176548 | Complementary analog bipolar transistors with trench-constrained isolation diffusion | Richard K. Williams, Wai Tien Chan | 2007-02-13 |
| 7135738 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology | Richard K. Williams, Wai Tien Chan | 2006-11-14 |
| 7084456 | Trench MOSFET with recessed clamping diode using graded doping | Richard K. Williams, Wai Tien Chan | 2006-08-01 |
| 7075145 | Poly-sealed silicide trench gate | Richard K. Williams, Wai Tien Chan | 2006-07-11 |
| 6969888 | Planarized and silicided trench contact | Richard K. Williams, Wai Tien Chan | 2005-11-29 |
| 6943426 | Complementary analog bipolar transistors with trench-constrained isolation diffusion | Richard K. Williams, Wai Tien Chan | 2005-09-13 |
| 6906386 | Testable electrostatic discharge protection circuits | Richard K. Williams, Wai Tien Chan | 2005-06-14 |
| 6900091 | Isolated complementary MOS devices in epi-less substrate | Richard K. Williams, Wai Tien Chan | 2005-05-31 |
| 6861701 | Trench power MOSFET with planarized gate bus | Richard K. Williams, Wai Tien Chan | 2005-03-01 |
| 6855985 | Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology | Richard K. Williams, Wai Tien Chan | 2005-02-15 |
| 6239463 | Low resistance power MOSFET or other device containing silicon-germanium layer | Richard K. Williams, Mohamed N. Darwish, Wayne B. Grabowski | 2001-05-29 |
| 5751054 | Zener diodes on the same wafer with BiCDMOS structures | Hamza Yilmaz, Richard K. Williams, Jun-Wei Chen | 1998-05-12 |
| 5726477 | Threshold adjustment in field effect semiconductor devices | Richard K. Williams | 1998-03-10 |
| 5648281 | Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate | Richard K. Williams, Hamza Yilmaz, Jun-Wei Chen | 1997-07-15 |
| 5648288 | Threshold adjustment in field effect semiconductor devices | Richard K. Williams | 1997-07-15 |
| 5643820 | Method for fabricating an MOS capacitor using zener diode region | Richard K. Williams, Hamza Yilmaz, Jun-Wei Chen | 1997-07-01 |
| 5618743 | MOS transistor having adjusted threshold voltage formed along with other transistors | Richard K. Williams, Hamza Yilmaz, Jun-Wei Chen | 1997-04-08 |
| 5583061 | PMOS transistors with different breakdown voltages formed in the same substrate | Richard K. Williams, Hamza Yilmaz, Jun-Wei Chen | 1996-12-10 |
| 5559044 | BiCDMOS process technology | Richard K. Williams, Hamza Yilmaz, Jun-Wei Chen | 1996-09-24 |
| 5547880 | Method for forming a zener diode region and an isolation region | Richard K. Williams, Hamza Yilmaz, Jun-Wei Chen | 1996-08-20 |