JD

Javier A. Delacruz

AT Adeia Semiconductor Bonding Technologies: 7 patents #7 of 42Top 20%
AS Adeia Semiconductor: 6 patents #1 of 9Top 15%
📍 San Jose, CA: #57 of 5,639 inventorsTop 2%
🗺 California: #525 of 55,090 inventorsTop 1%
Overall (2025): #3,634 of 469,880Top 1%
13
Patents 2025

Issued Patents 2025

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDate
12431449 Circuitry for electrical redundancy in bonded structures Belgacem Haba, Jung Ko 2025-09-30
12401010 3D processor having stacked integrated circuit die Steven Teig, Ilyas Mohammed, Kenneth Duong 2025-08-26
12362182 Direct-bonded native interconnects and active base die Steven Teig, Shaowu Huang, William C. Plants, David Edward Fisch 2025-07-15
12308332 Circuitry for electrical redundancy in bonded structures Belgacem Haba, Jung Ko 2025-05-20
12293993 3D chip sharing data bus Steven Teig, Ilyas Mohammed 2025-05-06
12293108 3D memory circuit David Edward Fisch 2025-05-06
12288771 Apparatus for non-volatile random access memory stacks Belgacem Haba, Rajesh Katkar, Pearl Po-Yee Cheng 2025-04-29
12283572 Symbiotic network on layers Belgacem Haba, Rajesh Katkar 2025-04-22
12278215 Integrated voltage regulator and passive components Don Draper, Belgacem Haba, Ilyas Mohammed 2025-04-15
12271032 Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects Shaowu Huang, Liang Wang, Guilian Gao 2025-04-08
12272730 Transistor level interconnection methodologies utilizing 3D interconnects David Edward Fisch 2025-04-08
12255176 Scalable architecture for reduced cycles across SOC Richard E. Perego 2025-03-18
12218059 Stacked IC structure with orthogonal interconnect layers Ilyas Mohammed, Steven Teig 2025-02-04