Issued Patents 2025
Showing 51–71 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12237414 | Source/drain features with improved strain properties | Chih-Ching Wang, Wen-Yuan Chen, Wen-Hsing Hsieh, Chung-Wei Wu, Zhiqiang Wu | 2025-02-25 |
| 12237405 | Semiconductor devices and methods of manufacturing thereof | Yi-Ruei Jhan, Kuan-Ting Pan, Kuo-Cheng Chiang, Chih-Hao Wang | 2025-02-25 |
| 12237372 | Field effect transistor and method | Lung-Kun Chu, Jia-Ni Yu, Chung-Wei Hsu, Chih-Hao Wang, Kuo-Cheng Chiang +1 more | 2025-02-25 |
| 12230572 | Backside signal interconnection | Yu-Xuan Huang, Ching-Wei Tsai, Yi-Hsun Chiu, Yi-Bo Liao, Wei-Cheng Lin +6 more | 2025-02-18 |
| 12224348 | Semiconductor device structure and method for forming the same | Kuo-Cheng Chiang, Shi Ning Ju, Ching-Wei Tsai, Chih-Hao Wang | 2025-02-11 |
| 12218136 | Semiconductor device having a Fin at a S/D region and a semiconductor contact or silicide interfacing therewith | Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang | 2025-02-04 |
| 12218224 | Method for forming semiconductor device | Wang-Chun Huang, Hou-Yu Chen, Chih-Hao Wang | 2025-02-04 |
| 12211922 | Gate air spacer for fin-like field effect transistor | Chien Ning Yao, Bo-Feng Young, Sai-Hooi Yeong, Chih-Hao Wang | 2025-01-28 |
| 12211921 | Method for forming FinFET devices with a fin top hardmask | Kuo-Cheng Ching, Kai-Chieh Yang, Ching-Wei Tsai, Chih-Hao Wang | 2025-01-28 |
| 12211790 | Conductive rail structure for semiconductor devices | Yi-Bo Liao, Wei Ju Lee, Cheng-Ting Chung, Hou-Yu Chen, Chun-Fu Cheng | 2025-01-28 |
| 12205896 | Contact via formation | Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang | 2025-01-21 |
| 12205848 | FinFET gate structure and related methods | Cheng-Ting Chung, Ching-Wei Tsai | 2025-01-21 |
| 12206005 | Semiconductor structures and methods thereof | Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu +1 more | 2025-01-21 |
| 12205985 | Field effect transistor with inactive fin and method | Yi-Ruei Jhan, Kuo-Cheng Chiang, Chih-Hao Wang | 2025-01-21 |
| 12199095 | Fin field effect transistors having vertically stacked nano-sheet | Wang-Chun Huang, Chih-Hao Wang, Ching-Wei Tsai | 2025-01-14 |
| 12199190 | Silicon channel tempering | Mao-Lin Huang, Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu, Chih-Hao Wang +1 more | 2025-01-14 |
| 12199097 | Seam free isolation structures and method for making the same | Yi-Ruei Jhan, Kuan-Ting Pan, Kuo-Cheng Chiang, Chih-Hao Wang | 2025-01-14 |
| 12199030 | Semiconductor devices including decoupling capacitors | Yu-Xuan Huang, Hou-Yu Chen, Ching-Wei Tsai, Chung-Hui Chen | 2025-01-14 |
| 12198754 | Timing control circuit of memory device with tracking word line and tracking bit line | Xiu-Li YANG, Lu-Ping KONG, He-Zhou WAN | 2025-01-14 |
| 12191305 | Integration of silicon channel nanostructures and silicon-germanium channel nanostructures | Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang, Guan-Lin Chen | 2025-01-07 |
| 12191307 | Multi-gate device and related methods | Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang | 2025-01-07 |