Issued Patents 2025
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12432954 | Semiconductor device structure with fin and method for forming the same | Kuo-An Liu, Kai Tak Lam, Meng-Yu Lin, Chun-Fu Cheng, Chieh-Chun Chiang +1 more | 2025-09-30 |
| 12414511 | Water sprinkler | Yuliang Zhu, Donglian Xie, Weimin He | 2025-09-16 |
| 12396240 | Source/drain silicide for multigate device performance and method of fabricating thereof | Chih-Ching Wang, Chung-I Yang, Jon-Hsu Ho, Wen-Hsing Hsieh, Chung-Wei Wu | 2025-08-19 |
| 12382691 | Effective work function tuning via silicide induced interface dipole modulation for metal gates | Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang +3 more | 2025-08-05 |
| 12376309 | Ferroelectric memory device and method of forming the same | Peng-Chun Liou, Chung-Wei Wu, Ya-Yun Cheng | 2025-07-29 |
| D1085489 | Downlight | — | 2025-07-22 |
| D1085501 | Downlight | — | 2025-07-22 |
| 12363908 | Semiconductor memory devices with varying channel width and methods of manufacturing thereof | Peng-Chun Liou, Ya-Yun Cheng, Yi-Ching Liu, Meng-Han Lin | 2025-07-15 |
| 12349418 | Semiconductor device and manufacturing method thereof | Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu | 2025-07-01 |
| 12349380 | Gate all around transistor device and fabrication methods thereof | Chih-Ching Wang, Chia-Ying Su, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu | 2025-07-01 |
| 12317526 | Multi-gate devices and fabricating the same with etch rate modulation | Chih-Ching Wang, Chung-I Yang, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng +1 more | 2025-05-27 |
| 12310029 | Semiconductor memory device and manufacturing method thereof | Yu-Chien Chiu, Meng-Han Lin, Chun-Fu Cheng, Han-Jong Chia, Chung-Wei Wu | 2025-05-20 |
| 12300721 | Semiconductor device structure with channel and method for forming the same | Huang-Siang LAN, Sathaiya Mahaveer DHANYAKUMAR, Tzer-Min Shen | 2025-05-13 |
| 12300749 | Source/drain features with improved strain properties | Chih-Ching Wang, Wen-Yuan Chen, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu | 2025-05-13 |
| 12300754 | Channel configurations with stacked segments for gate-all-around based devices and methods of fabrication thereof | Chih-Ching Wang, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng | 2025-05-13 |
| 12302640 | Integrated circuit structure and method with hybrid orientation for FinFET | Tzer-Min Shen, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang +1 more | 2025-05-13 |
| 12272043 | Semiconductor topography simulation of non-removal type processes | Zhengping Jiang, Nuo Xu, Ji-Ting Li, Yuan-Hao Chang, Wen-Hsing Hsieh | 2025-04-08 |
| 12256551 | Method for forming semiconductor memory structure | Nuo Xu, Sai-Hooi Yeong, Yu-Ming Lin | 2025-03-18 |
| 12237414 | Source/drain features with improved strain properties | Chih-Ching Wang, Wen-Yuan Chen, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu | 2025-02-25 |
| 12218214 | Source/drain silicide for multigate device performance and method of fabricating thereof | Chih-Ching Wang, Chung-I Yang, Jon-Hsu Ho, Wen-Hsing Hsieh, Chung-Wei Wu | 2025-02-04 |
| 12217782 | Current steering in reading magnetic tunnel junction | Gaurav Gupta, Yih Wang | 2025-02-04 |
| 12199170 | Method of manufacturing a multi-gate device having a semiconductor seed layer embedded in an isolation layer | Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu | 2025-01-14 |
| 12190931 | Semiconductor memory devices and methods of manufacturing thereof | Peng-Chun Liou, Chung-Wei Wu, Yi-Ching Liu, Yih Wang | 2025-01-07 |