Issued Patents 2025
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12262643 | Techniques for MRAM MTJ top electrode connection | Chern-Yow Hsu, Shih-Chang Liu | 2025-03-25 |
| 12255133 | Electrical fuse (e-fuse) one-time programmable (OTP) device and manufacturing method thereof | Alexander Kalnitsky, Wei-Cheng Wu, Chia-Wen Liang, Li-Feng Teng | 2025-03-18 |
| 12256647 | Embedded MRAM fabrication process for ion beam etching with protection by top electrode spacer | Jun Chen, Hung Cho Wang | 2025-03-18 |
| 12250826 | Integrated circuit device and method for fabricating the same | Yuan-Jen Lee, Tien-Wei Chiang, Hung Cho Wang, Kuei-Hung Shen, Sheng-Huang Huang | 2025-03-11 |
| 12250888 | Method and structure for improved memory integrity at array boundaries | Jun Chen, Hung Cho Wang | 2025-03-11 |
| 12245437 | Semiconductor device | Wu-Chang Tsai, Tien-Wei Chiang | 2025-03-04 |
| 12223989 | Semiconductor device and method for fabricating the same | Sheng-Huang Huang, Hung Cho Wang, Sheng-Chang Chen | 2025-02-11 |
| 12217975 | Semiconductor device having metal gate and poly gate | Alexander Kalnitsky, Wei-Cheng Wu | 2025-02-04 |
| 12218074 | DC and AC magnetic field protection for MRAM device using magnetic-field-shielding structure | Tien-Wei Chiang, Kuo-An Liu, Chia-Hsiang Chen | 2025-02-04 |
| 12210055 | Semiconductor wafer testing system and related method for improving external magnetic field wafer testing | Chih-Yang Chang, Ching-Huang Wang, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang | 2025-01-28 |
| 12191262 | Package structure and method for fabricating the same | Chia-Hsiang Chen, Meng-Chun Shih, Ching-Huang Wang, Tien-Wei Chiang | 2025-01-07 |
| 12191282 | Shared pad/bridge layout for a 3D IC | Wei-Cheng Wu, Wen-Tuo Huang, Chia-Sheng Lin, Wei Chuang Wu, Shih Kuang Yang +5 more | 2025-01-07 |