Issued Patents 2025
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430243 | Using a common pool of blocks for user data and a system data structure | Kishore Kumar Muchherla, Kulachet Tanpairoj, Peter Feeley, Ashutosh Malshe | 2025-09-30 |
| 12424287 | Memory read voltage threshold tracking based on memory device-originated metrics characterizing voltage distributions | Shantilal Rayshi Doru, Patrick R. Khayat, Steven Michael Kientz, Dung Viet Nguyen | 2025-09-23 |
| 12393363 | Voltage bin calibration based on a voltage distribution reference voltage | Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Mustafa N. Kaynak, Peter Feeley +2 more | 2025-08-19 |
| 12353753 | Diagonal page mapping in memory systems | Tawalin Opastrakoon, Renato C. Padilla, Michael G. Miller, Christopher M. Smitchger, Gary F. Besinga +1 more | 2025-07-08 |
| 12332742 | Memory compaction management in memory devices | Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Patrick R. Khayat, Kishore Kumar Muchherla +2 more | 2025-06-17 |
| 12307121 | Filtering metrics associated with memory | Dung Viet Nguyen, Shantilal Rayshi Doru, Jun Wan | 2025-05-20 |
| 12229000 | Managing error-handling flows in memory devices | Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Peter Feeley, Sivagnanam Parthasarathy +2 more | 2025-02-18 |
| 12216573 | Memory device with dynamic cache management | Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale +3 more | 2025-02-04 |