Issued Patents 2025
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431202 | Memory read calibration based on memory device-originated metrics characterizing voltage distributions | Patrick R. Khayat, Zhengang Chen, Shantilal Rayshi Doru, Hope Henry | 2025-09-30 |
| 12424287 | Memory read voltage threshold tracking based on memory device-originated metrics characterizing voltage distributions | Shantilal Rayshi Doru, Patrick R. Khayat, Steven Michael Kientz, Sampath K. Ratnam | 2025-09-23 |
| 12332743 | Efficient memory use to support soft information in bit flipping decoders | Mustafa N. Kaynak, Eyal En Gad, Zhengang Chen, Sivagnanam Parthasarathy, Phong Sy Nguyen | 2025-06-17 |
| 12334153 | Adaptive pre-read management in multi-pass programming | Kishore Kumar Muchherla, Huai-Yuan Tseng, Akira Goda, Giovanni Maria Paolucci, James Fitzpatrick +3 more | 2025-06-17 |
| 12307090 | Memory device programming technique for increased bits per cell | Tomoharu Tanaka, Huai-Yuan Tseng, Kishore Kumar Muchherla, Eric N. Lee, Akira Goda +2 more | 2025-05-20 |
| 12307121 | Filtering metrics associated with memory | Shantilal Rayshi Doru, Jun Wan, Sampath K. Ratnam | 2025-05-20 |
| 12277978 | Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices | James Fitzpatrick, Phong Sy Nguyen, Sivagnanam Parthasarathy | 2025-04-15 |
| 12266407 | Conditional valley tracking during corrective reads | Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Kishore Kumar Muchherla, Eric N. Lee +2 more | 2025-04-01 |
| 12249364 | Apparatus with non-linear delay variations for scheduling memory refresh operations and methods for operating the same | Huai-Yuan Tseng, Akira Goda, Kishore Kumar Muchherla, James Fitzpatrick, Tomoharu Tanaka +2 more | 2025-03-11 |