Issued Patents 2025
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12373286 | Handling non-correctable errors | Abhijeet Ashok Chachad | 2025-07-29 |
| 12332790 | Multi-level cache security | Abhijeet Ashok Chachad, Naveen Bhoria | 2025-06-17 |
| 12321270 | Hardware coherence for memory controller | Abhijeet Ashok Chachad, Naveen Bhoria | 2025-06-03 |
| 12321277 | Prefetch management in a hierarchical cache system | Bipin Prasad Heremagalur Ramaprasad, Abhijeet Ashok Chachad, Hung Ong | 2025-06-03 |
| 12271314 | Cache size change | Abhijeet Ashok Chachad, Naveen Bhoria, Neelima Muralidharan | 2025-04-08 |
| 12217102 | Distributed mechanism for fine-grained test power control | Devanathan Varadarajan, Varun Singh, Jose Luis Flores, Rejitha Nair | 2025-02-04 |
| 12197332 | Memory pipeline control in a hierarchical memory system | Abhijeet Ashok Chachad, Timothy David Anderson, Kai Chirca | 2025-01-14 |
| 12197331 | Hardware coherence signaling protocol | Abhijeet Ashok Chachad, Naveen Bhoria, Pete Michael Hippleheuser | 2025-01-14 |