AN

Ankireddy Nalamalpu

IN Intel: 14 patents #43 of 3,896Top 2%
Overall (2025): #2,819 of 469,880Top 1%
15
Patents 2025

Issued Patents 2025

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDate
12431899 Self-gating flops for dynamic power reduction Mahesh Kumashikar, MD Altaf Hossain, Yuet-Wing Li, Atul Maheshwari 2025-09-30
12429900 Controlled transition between configuration mode and user mode to reduce current-resistance voltage drop Atul Maheshwari, Mahesh A. Iyer, Mahesh Kumashikar 2025-09-30
12422477 Segmented row repair for programmable logic devices Dheeraj Subbareddy, Arun Jangity, Ramya Yeluri, Mahesh Kumashikar, Atul Maheshwari 2025-09-23
12379698 Systems and methods to reduce voltage guardband Mahesh Kumashikar, MD Altaf Hossain, Mahesh A. Iyer, Yuet-Wing Li, Atul Maheshwari 2025-08-05
12353238 Flexible instruction set architecture supporting varying frequencies Dheeraj Subbareddy, Anshuman Thakur, Atul Maheshwari, Mahesh Kumashikar, MD Altaf Hossain 2025-07-08
12355359 Switch based on load current MD Altaf Hossain, Mahesh Kumashikar, Dheeraj Subbareddy, Atul Maheshwari, Mahesh A. Iyer 2025-07-08
12347783 Interconnect architecture with silicon interposer and EMIB MD Altaf Hossain, Dheeraj Subbareddy, Robert Sankman, Ravindranath V. Mahajan, Debendra Mallik +7 more 2025-07-01
12341511 Power management using voltage islands on programmable logic devices Mahesh Kumashikar, MD Altaf Hossain, Dheeraj Subbareddy, Atul Maheshwari, Yuet-Wing Li +1 more 2025-06-24
12334449 Selective use of different advanced interface bus with electronic chips Dheeraj Subbareddy, Lai Guan Tang, Mahesh Kumashikar 2025-06-17
12294368 Three-dimensional stacked programmable logic fabric and processor design architecture Rahul Pal, Dheeraj Subbareddy, Mahesh Kumashikar, Dheemanth Nagaraj, Rajesh Vivekanandham +3 more 2025-05-06
12273107 Dynamically scalable timing and power models for programmable logic devices Atul Maheshwari, Mahesh A. Iyer, Mahesh Kumashikar, Ian Kuon, Yuet-Wing Li +1 more 2025-04-08
12266625 Innovative interconnect design for package architecture to improve latency MD Altaf Hossain, Dheeraj Subbareddy 2025-04-01
12237831 Network-on-chip (NOC) with flexible data width Sharath Raghava, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad +1 more 2025-02-25
12216150 On-die aging measurements for dynamic timing modeling Dheeraj Subbareddy, Mahesh A. Iyer, Dhananjay Raghavan 2025-02-04
12206410 Programmable logic device with fine-grained disaggregation Dheeraj Subbareddy, MD Altaf Hossain, Robert Sankman, Ravindranath V. Mahajan, Gregg William Baeckler 2025-01-21