Issued Patents 2025
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431899 | Self-gating flops for dynamic power reduction | MD Altaf Hossain, Yuet-Wing Li, Atul Maheshwari, Ankireddy Nalamalpu | 2025-09-30 |
| 12429900 | Controlled transition between configuration mode and user mode to reduce current-resistance voltage drop | Atul Maheshwari, Ankireddy Nalamalpu, Mahesh A. Iyer | 2025-09-30 |
| 12422477 | Segmented row repair for programmable logic devices | Dheeraj Subbareddy, Arun Jangity, Ramya Yeluri, Atul Maheshwari, Ankireddy Nalamalpu | 2025-09-23 |
| 12379698 | Systems and methods to reduce voltage guardband | MD Altaf Hossain, Mahesh A. Iyer, Yuet-Wing Li, Atul Maheshwari, Ankireddy Nalamalpu | 2025-08-05 |
| 12353238 | Flexible instruction set architecture supporting varying frequencies | Dheeraj Subbareddy, Anshuman Thakur, Atul Maheshwari, MD Altaf Hossain, Ankireddy Nalamalpu | 2025-07-08 |
| 12355359 | Switch based on load current | MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Atul Maheshwari, Mahesh A. Iyer | 2025-07-08 |
| 12341511 | Power management using voltage islands on programmable logic devices | Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Atul Maheshwari, Yuet-Wing Li +1 more | 2025-06-24 |
| 12334449 | Selective use of different advanced interface bus with electronic chips | Dheeraj Subbareddy, Ankireddy Nalamalpu, Lai Guan Tang | 2025-06-17 |
| 12321714 | Compressed wallace trees in FMA circuits | Aditya Varma, Michael Espig | 2025-06-03 |
| 12294368 | Three-dimensional stacked programmable logic fabric and processor design architecture | Rahul Pal, Dheeraj Subbareddy, Dheemanth Nagaraj, Rajesh Vivekanandham, Anshuman Thakur +3 more | 2025-05-06 |
| 12273107 | Dynamically scalable timing and power models for programmable logic devices | Atul Maheshwari, Mahesh A. Iyer, Ian Kuon, Yuet-Wing Li, Ankireddy Nalamalpu +1 more | 2025-04-08 |