Issued Patents 2025
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430489 | Restructuring algorithm for including user-specified clock instances in a post-CTS clock tree | Andrew Mark Chapman, Ruth Patricia Jackson | 2025-09-30 |
| 12423501 | Skewing level limited clock tree | Andrew Mark Chapman, Andrew Hall | 2025-09-23 |
| 12423499 | Resistance and capacitance aware preferred layer trimming | Derong Liu, Mehmet Can Yildiz | 2025-09-23 |
| 12393763 | Timing-based layer assignment | Derong Liu, Wing-Kai Chow, Mehmet Can Yildiz | 2025-08-19 |
| 12393760 | Wire density-aware layer assignment | Derong Liu, Wing-Kai Chow, Gracieli Posser, Mehmet Can Yildiz | 2025-08-19 |
| 12339701 | Insertion delay and area tradeoff for buffering solution selection in clock tree synthesis | Yi-Xiao Ding, Sheng-En David Lin, Natarajan Viswanathan | 2025-06-24 |
| 12321193 | Hierarchically-aware buffering for clock structures | Yi-Xiao Ding, Sheng-En David Lin, Natarajan Viswanathan | 2025-06-03 |