NV

Natarajan Viswanathan

CS Cadence Design Systems: 2 patents #9 of 106Top 9%
🗺 Texas: #1,899 of 13,174 inventorsTop 15%
Overall (2025): #98,249 of 469,880Top 25%
2
Patents 2025

Issued Patents 2025

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
12339701 Insertion delay and area tradeoff for buffering solution selection in clock tree synthesis Yi-Xiao Ding, Sheng-En David Lin, Charles J. Alpert 2025-06-24
12321193 Hierarchically-aware buffering for clock structures Yi-Xiao Ding, Sheng-En David Lin, Charles J. Alpert 2025-06-03