Issued Patents 2024
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12154970 | Method for semiconductor device structure | Tze-Chung Lin, Li-Te Lin, Pinyen Lin | 2024-11-26 |
| 12136660 | Semiconductor device, and method for protecting low-k dielectric feature of semiconductor device | Cheng-Ming Lin, Wei-Yen Woon, Mrunal A. Khaderbad | 2024-11-05 |
| 12136570 | Graphene layer for low resistance contacts and damascene interconnects | Mrunal A. Khaderbad, Wei-Yen Woon, Cheng-Ming Lin, Szu-Hua Chen, Jhih-Rong Huang +1 more | 2024-11-05 |
| 12062576 | Semiconductor devices with a rare earth metal oxide layer | Szu-Hua Chen, Kuan-Kan Hu, Kenichi Sano, Po-Cheng Wang, Wei-Yen Woon +2 more | 2024-08-13 |
| 12046676 | Semiconductor devices and methods of manufacturing thereof | Yu-Lien Huang, Yi-Shan Chen, Kuan Da Huang, Li-Te Lin, Ming-Huan Tsai | 2024-07-23 |
| 12033863 | Semiconductor fabrication system embedded with effective baking module | Yi-Ruei Jhan, Fang-Wei Lee, Li-Te Lin, Pinyen Lin, Tze-Chung Lin | 2024-07-09 |
| 12021125 | High selectivity etching with germanium-containing gases | Tze-Chung Lin, Pinyen Lin, Fang-Wei Lee, Li-Te Lin | 2024-06-25 |
| 11973129 | Semiconductor device structure with inner spacer layer and method for forming the same | Chansyun David Yang, Fang-Wei Lee, Tze-Chung Lin, Li-Te Lin, Pinyen Lin | 2024-04-30 |
| 11908685 | Methods of reducing gate spacer loss during semiconductor manufacturing | Yi-Ruei Jhan, Li-Te Lin, Pinyen Lin | 2024-02-20 |