Issued Patents 2024
Showing 26–28 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11887670 | Controlling bit line pre-charge voltage separately for multi-level memory cells and single-level memory cells to reduce peak current consumption | Yu-Chung Lien, Deepanshu Dutta | 2024-01-30 |
| 11875043 | Loop dependent word line ramp start time for program verify of multi-level NAND memory | Abu Naser Zainuddin, Toru Miwa | 2024-01-16 |
| 11862249 | Non-volatile memory with staggered ramp down at the end of pre-charging | Xiang Yang, Fanqi Wu, Jiacen Guo | 2024-01-02 |