Issued Patents 2024
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183393 | High-speed multi-port memory supporting collision | Pradeep Raj, Rahul Sahu | 2024-12-31 |
| 12047073 | Power supply circuit with reduced leakage current | Pradeep Raj, Rahul Sahu, Chulmin Jung | 2024-07-23 |
| 12020766 | Memory circuit architecture with multiplexing between memory banks | Pradeep Raj, Rahul Sahu, Hemant Patel, Diwakar SINGH | 2024-06-25 |
| 11979167 | Low power and high speed data weighted averaging (DWA) to binary converter circuit | Ankur Bal | 2024-05-07 |
| 11972834 | Low power and robust level-shifting pulse latch for dual-power memories | Adithya Bhaskaran, Rahul Sahu | 2024-04-30 |
| 11955169 | High-speed multi-port memory supporting collision | Pradeep Raj, Rahul Sahu | 2024-04-09 |
| 11935606 | Memory with scan chain testing of column redundancy logic and multiplexing | Rahul Sahu, Jung Pill Kim, Chulmin Jung, Jais Abraham | 2024-03-19 |
| 11933861 | Phase-independent testing of a converter | Ankur Bal | 2024-03-19 |
| 11909410 | Sigma-delta analog-to-digital converter circuit with real time correction for digital-to-analog converter mismatch error | Ankur Bal | 2024-02-20 |
| 11901919 | On chip test architecture for continuous time delta sigma analog-to-digital converter | Ankur Bal, Abhishek Jain | 2024-02-13 |