Issued Patents 2024
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183424 | Bit-cell architecture based in-memory compute | Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-12-31 |
| 12176025 | Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-12-24 |
| 12170120 | Built-in self test circuit for segmented static random access memory (SRAM) array input/output | Hitesh Chawla, Tanuj KUMAR, Bhupender Singh, Kedar Janardan Dhori, Manuj AYODHYAWASI +2 more | 2024-12-17 |
| 12159689 | SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications | Praveen Kumar Verma, Promod Kumar | 2024-12-03 |
| 12087356 | Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-09-10 |
| 12068026 | Low power and fast memory reset | Praveen Kumar Verma | 2024-08-20 |
| 12046324 | Modular memory architecture with gated sub-array operation dependent on stored data content | Praveen Kumar Verma, Promod Kumar, Christophe Lecocq | 2024-07-23 |
| 12040013 | Static random access memory supporting a single clock cycle read-modify-write operation | Praveen Kumar Verma | 2024-07-16 |
| 11984151 | Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-05-14 |